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Fri, 16 May 2025 07:09:32 -0400 (EDT) Date: Fri, 16 May 2025 14:09:28 +0300 From: "Kirill A. Shutemov" To: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= Cc: "Kirill A. Shutemov" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Jonathan Corbet , Andy Lutomirski , Peter Zijlstra , Ard Biesheuvel , Jan Kiszka , Kieran Bingham , Michael Roth , Rick Edgecombe , Brijesh Singh , Sandipan Das , Tom Lendacky , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional Message-ID: References: <20250516091534.3414310-1-kirill.shutemov@linux.intel.com> <20250516091534.3414310-4-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Rspamd-Server: rspam10 X-Stat-Signature: j7xjzmpx9snjkrzmgb16thx8cg8d6d96 X-Rspamd-Queue-Id: 8EB511A0004 X-Rspam-User: X-HE-Tag: 1747393782-145997 X-HE-Meta: U2FsdGVkX1/j96DSmYb0egaQMOFi7VPfqHVeD8og5VUnGPqcOotC6mLn5wRA0TD3TWgj3DqwIlQyjdXVjDtZobx6nlC+tfzODaQHrxey8VXDsW7/FqmPaFjxTCrC5f5Ib+4TlZEGNlihZqf9h15rqEj6PFzFLv1s+kUW0hCmZHD+MRhT+zTjmwg6raxuH8Y+pRTLxiGusJCyz3t0teTTxz7sxD7L9ojqo19sUMpQajE4lQ79kFrKUXdLJwHF7+nxzJzdVfJRL3SL0MNkzc23/VJWmwxzjIL5uWE8NEBKBILikNRj9zSOSBytvzLw9m1dNsMxilbNHlyT7E69omgYLArRRwQyv1LBWTmwGL8gF3Nm5ey04tPPMy22O/CxzmTuHBGqOUOBcloIE8JT2dkd3cqfjwjfDik6vaeALPYFjE7DMw1jCu99sfF33d7zBxeQg6wplZB8slxKg1Whdjr4Bntz+A82XyirDwXMj32FQqE2p2U5dFngnOFU8IsO0BjySL4WZXPSRDTZZRMLzwsPF9Fl56jZvsQEv7+piMDCCB1T3HMfm9bqIBAzqFSfUmMpPgPhnIXRUHz9hxLXZG1hRoxkCIvu4lbdVFTZghmZMjvxka3EDokYAo/8gUTQdqyfJkJXR+w01e+qrZTSVfEK4nKcAh75OuedYjpZ/OWlqdft8LKbPxPLefICY6ONW2Rh3NVnjleWzWITCHgtXNlsciimHFlfhiVRcp2R3Qt1UzA//oYkED/FdgigKTqo8L0/L3554AcNBiL+EIcAl0HoDhA5eaglfqLPnkfDmD0rByJS4qE3jvQOaXqP1CvUJv6e4rL8KlrJI1nJMuCYkrQvgKW5DaJ5mWP10cL4KWJpxHf8k/nBOHVnBu0yhROz/4I1MDyIxgvxzsGc8xObz/MkWtFjvqIT6nDXK4owHgy69FtYuMv/ceiHbdRBNs9LqU1OlLXGAeEYUTc6s85k3Yx Z0xnlJ+W SsdDI4yIoq7iWrQOa3SzG0Q6Wg6fH66S6PgHfzxgXTTU7u8Qr+6Z5QMwVzFm8KDMz/chzgGm1Pt26pmueMWpIYzoxcQ73eRzvHJXRrPMDF1NhUK1CrbWXHTWtTMjLDdbt9R/9H7IanxeqgYgpYMUSLN9/vybvdyCL0aiWcoyE24HZyVPN3fZmIVCF0CaEG+KfB3c8XCBoDJLFM02QBg+nYyjQmOBPT2q0wxDQdHoMKrbSx6UVDKRpWOJFsVaJHc8iDRABLHDtI/wgRv/+tkC3/o0o7OffDs3F59eTtAh9qf0bzKE3JToiwNM/j56UfX9hDathIdtBZSm/wGRfvjNQl5QvbXM4lvyJsjnsV2iUZKmbJTBGPpArKiTDAWul8xEXKW83ZekrmS3ge7+nn5qcP3AX6G4NZFxTlImFzm8F8PzggPWkWphPgETK6BLBSqnXD58CTMIsE1RpZ2A= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote: > On 16.05.25 11:15, Kirill A. Shutemov wrote: > > Both Intel and AMD CPUs support 5-level paging, which is expected to > > become more widely adopted in the future. > > > > Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable. > > > > Signed-off-by: Kirill A. Shutemov > > Suggested-by: Borislav Petkov > > --- > > Documentation/arch/x86/cpuinfo.rst | 8 +++---- > > .../arch/x86/x86_64/5level-paging.rst | 9 -------- > > arch/x86/Kconfig | 22 +------------------ > > arch/x86/Kconfig.cpufeatures | 4 ---- > > arch/x86/boot/compressed/pgtable_64.c | 11 ++-------- > > arch/x86/boot/header.S | 4 ---- > > arch/x86/boot/startup/map_kernel.c | 5 +---- > > arch/x86/include/asm/page_64.h | 2 -- > > arch/x86/include/asm/page_64_types.h | 7 ------ > > arch/x86/include/asm/pgtable_64_types.h | 18 --------------- > > arch/x86/kernel/alternative.c | 2 +- > > arch/x86/kernel/head64.c | 2 -- > > arch/x86/kernel/head_64.S | 2 -- > > arch/x86/mm/init.c | 4 ---- > > arch/x86/mm/pgtable.c | 2 +- > > drivers/firmware/efi/libstub/x86-5lvl.c | 2 +- > > 16 files changed, 10 insertions(+), 94 deletions(-) > > There are some instances of: > > #if CONFIG_PGTABLE_LEVELS >= 5 > > in 64-bit-only code under arch/x86, which could be simplified, too. > > They are still correct, but I wanted to hint at further code removals > being possible. Okay, fair enough. Fixup is below. Did I miss anything else? diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c index 2fb7d53cf333..c9103a6fa06e 100644 --- a/arch/x86/entry/vsyscall/vsyscall_64.c +++ b/arch/x86/entry/vsyscall/vsyscall_64.c @@ -341,9 +341,7 @@ void __init set_vsyscall_pgtable_user_bits(pgd_t *root) pgd = pgd_offset_pgd(root, VSYSCALL_ADDR); set_pgd(pgd, __pgd(pgd_val(*pgd) | _PAGE_USER)); p4d = p4d_offset(pgd, VSYSCALL_ADDR); -#if CONFIG_PGTABLE_LEVELS >= 5 set_p4d(p4d, __p4d(p4d_val(*p4d) | _PAGE_USER)); -#endif pud = pud_offset(p4d, VSYSCALL_ADDR); set_pud(pud, __pud(pud_val(*pud) | _PAGE_USER)); pmd = pmd_offset(pud, VSYSCALL_ADDR); diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index b89f8f1194a9..f06e5d6a2747 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -41,11 +41,9 @@ static inline void sync_initial_page_table(void) { } pr_err("%s:%d: bad pud %p(%016lx)\n", \ __FILE__, __LINE__, &(e), pud_val(e)) -#if CONFIG_PGTABLE_LEVELS >= 5 #define p4d_ERROR(e) \ pr_err("%s:%d: bad p4d %p(%016lx)\n", \ __FILE__, __LINE__, &(e), p4d_val(e)) -#endif #define pgd_ERROR(e) \ pr_err("%s:%d: bad pgd %p(%016lx)\n", \ diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index 38971c6dcd4b..61c52bb80e33 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -578,7 +578,6 @@ static void xen_set_p4d(p4d_t *ptr, p4d_t val) xen_mc_issue(XEN_LAZY_MMU); } -#if CONFIG_PGTABLE_LEVELS >= 5 __visible p4dval_t xen_p4d_val(p4d_t p4d) { return pte_mfn_to_pfn(p4d.p4d); @@ -592,7 +591,6 @@ __visible p4d_t xen_make_p4d(p4dval_t p4d) return native_make_p4d(p4d); } PV_CALLEE_SAVE_REGS_THUNK(xen_make_p4d); -#endif /* CONFIG_PGTABLE_LEVELS >= 5 */ static void xen_pmd_walk(struct mm_struct *mm, pmd_t *pmd, void (*func)(struct mm_struct *mm, struct page *, -- Kiryl Shutsemau / Kirill A. Shutemov