From: Palmer Dabbelt <palmer@dabbelt.com>
To: nadav.amit@gmail.com
Cc: alexghiti@rivosinc.com, Will Deacon <will@kernel.org>,
aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org,
npiggin@gmail.com, peterz@infradead.org,
mchitale@ventanamicro.com, vincent.chen@sifive.com,
Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, linux-arch@vger.kernel.org,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, samuel@sholland.org,
prabhakar.csengg@gmail.com
Subject: Re: [PATCH v6 0/4] riscv: tlb flush improvements
Date: Mon, 06 Nov 2023 23:00:03 -0800 (PST) [thread overview]
Message-ID: <mhng-4e3e3fa7-5e25-494c-a3ad-6ef7ec78cf20@palmer-ri-x1c9a> (raw)
In-Reply-To: <24E0FC81-810E-44FD-9494-CA9374E495B5@gmail.com>
On Mon, 30 Oct 2023 07:01:48 PDT (-0700), nadav.amit@gmail.com wrote:
>
>> On Oct 30, 2023, at 3:30 PM, Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>>
>> + on_each_cpu_mask(cmask,
>> + __ipi_flush_tlb_range_asid,
>> + &ftd, 1);
>>
>
> Unrelated, but having fed
Do you mean `ftd`?
If so I'm not all that convinced that's a problem: sure it's 4x`long`,
so we pass it on the stack instead of registers, but otherwise we'd need
another `on_each_cpu_mask()` callback to shim stuff through via
registers.
> on the stack might cause it to be unaligned to
> the cacheline, which in x86 we have seen introduces some overhead.
We have 128-bit stack alignment on RISC-V, so the elements are at least
aligned. Since they're just being loaded up as scalars for the next
function call I'm not sure the alignment is all that exciting here.
> Actually, it is best not to put it on the stack, if possible to reduce
> cache traffic.
Sorry if I'm just missing something, but I'm not convinced this is a
measurable performance problem.
next prev parent reply other threads:[~2023-11-07 7:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 13:30 Alexandre Ghiti
2023-10-30 13:30 ` [PATCH v6 1/4] riscv: Improve tlb_flush() Alexandre Ghiti
2023-10-30 13:30 ` [PATCH v6 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
2023-10-30 13:30 ` [PATCH v6 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-10-30 13:30 ` [PATCH v6 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
2023-10-30 14:01 ` [PATCH v6 0/4] riscv: tlb flush improvements Nadav Amit
2023-11-07 7:00 ` Palmer Dabbelt [this message]
2023-11-07 8:38 ` Nadav Amit
2023-11-07 6:50 ` patchwork-bot+linux-riscv
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