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Tue, 14 Mar 2023 22:23:43 -0700 (PDT) Date: Tue, 14 Mar 2023 22:23:43 -0700 (PDT) X-Google-Original-Date: Tue, 14 Mar 2023 22:22:49 PDT (-0700) Subject: Re: [PATCH v3 20/34] riscv: Implement the new page table range API In-Reply-To: <20230228213738.272178-21-willy@infradead.org> CC: linux-mm@kvack.org, linux-arch@vger.kernel.org, willy@infradead.org, linux-kernel@vger.kernel.org, alexghiti@rivosinc.com, Paul Walmsley , aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org From: Palmer Dabbelt To: willy@infradead.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Rspam-User: X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 543731C000F X-Stat-Signature: 84neppfifp8dfkyfijkzxf7yzx77u8w4 X-HE-Tag: 1678857825-411693 X-HE-Meta: U2FsdGVkX1/cKoYd1wDDm8USdhT2L9kaxms/yX+KeJWu8wHoIBYxEkgsKvhEzbl8V65olySBWbE9f6kpxMhqak6DApAf+KxyGAYFfOop2q0PccZp5E4ffFKXuX+PConoothRu/tfbEINvpNnIENYVmnAzgnOgzulzAus8/dl3hwO0g+6nV9QcpkvWIocAnc+UPoeqby1+vucNBpr84FW842kztFAJDD7ja3vHpfS+RqhzWMfGGwZNzBJ0nGJufCQuXn1cz4+WReGo50hZMr2v3/b2MmHOi6ht59w0LoshxMxagKMg1Ls/7+0JtiqqoFsxqdtiEwmqU2kfaUhVnbsWpS8Zu6y3SHniK+XizUrftGomu4r3cNRJ+EQN/Q4zGq91fFFpYSwQMPkj4TlSML+KgLRNCMNQi76MLIIFQQ5GVK2XHk/fhAZKQAhLbuzXme30VhvM0E21o+sj9U4Ae9I5rIR5l1FLj5Zpsr0xVVXME6DFfANLkByWcx7xQXKFS5L0RVwwN9VlW73Te3Xb4uUOKuVlW+U2a8SRVsyhXirPQDBBxgNIsNuILhKzdGd0U40DdG/L3BAj/TjfF4wJpU0T4/CmBv2Wc1N0vyxz0VTQPgQNUKtlcroAPz++pBF7EtVzj/L9XqbKMrUo/PPNswJtdEEThoyWrKLyNzNKUzPV6K0T2yIF3Z8Sl7G+RSw6JFNtTrA47LgWIaKKObAB7Deq/uZs4+PmEp0MVBvH8kT+jGyk6iWxoIJoYhCAzCh3klzLzfMX0alAzBCZdfLF1c8KMvFo77lcMqxiSg9KhXUKOZxUc2OEg7kh6Lss6DEoDXBFDXA3Sc7hJD+on/XyFBF83UGZHRPhc8+aZExN8zZ2Go3reiqzp/Kg3KG2CiA8E7EDl3a8Z120OGs4MrSDZP7fk0UjvzD8nE9RjAm7MWY1k+AThq4qJyRp4jHX1H5CXWCnLh93uk3FBBi6tuarC8 zzPvl3PX hsa5Z36VquZiGJXQ6YhDvX6Yvq65Ak4LdsvhaKEQzKwPB8HqQxcWDsGQLzynol2tR/YQCeWLTmLUCr8cWRKkhZD2/VCejkL2gdINYw0EC+ha3TDWacXC9uIye7BSddZEqkYVwcBU0xyd2oijawZNP0TsTJp3yFozF1hziCLFxYvlR2MhY7AbSyzOPYns3UhC2UfBOiu83nD0ft8WoRXPZfde2iM10dkY3ql3v9DNH6+D3fBDMLUSPSe59n/loWJD+80gl3T9HxfS6JKY21ttiTMT0I/3UiPvggpXIYvHTfuVz7uHIqnrZyMoQ9n5MR6V+Q9V87Nj/EMmMeak6fUu66UR4L7+7BYyAboN1dy/DQQ716N49IJpX2ORtZbbXSYtc3BWq3V+BFGg3SfPNNr+ZyoV3+QDHj6ygYe96r52VmewgNnMHE0bXJsSMEa+XTW8zLReKCY7SE17jku91uZtWkmcOxtvhsBQ32qqM+e1m4IjCZLYJZ+3jVizD98XbSsexlMXcAXR0zTMY94LJb2V3OZdqzpuqGr9JPi2lr0vKrbPkMWj0UIkdEHPTtLorqztIcdpasvF3jHHNyEhnaQgOMwUgSfs09RkLQp6Tz9RpqyYWp1x2zEPeh/fQcQ/d8uFm6Km5efmou91xO7gu4SIiglTrYdV+I4Zf9vtA X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, 28 Feb 2023 13:37:23 PST (-0800), willy@infradead.org wrote: > Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). > Change the PG_dcache_clean flag from being per-page to per-folio. > > Signed-off-by: Matthew Wilcox (Oracle) > Reviewed-by: Alexandre Ghiti > Cc: Paul Walmsley > Cc: Palmer Dabbelt > Cc: Albert Ou > Cc: linux-riscv@lists.infradead.org > --- > arch/riscv/include/asm/cacheflush.h | 19 +++++++++---------- > arch/riscv/include/asm/pgtable.h | 26 +++++++++++++++++++------- > arch/riscv/mm/cacheflush.c | 11 ++--------- > 3 files changed, 30 insertions(+), 26 deletions(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index 03e3b95ae6da..10e5e96f09b5 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -15,20 +15,19 @@ static inline void local_flush_icache_all(void) > > #define PG_dcache_clean PG_arch_1 > > -static inline void flush_dcache_page(struct page *page) > +static inline void flush_dcache_folio(struct folio *folio) > { > - /* > - * HugeTLB pages are always fully mapped and only head page will be > - * set PG_dcache_clean (see comments in flush_icache_pte()). > - */ > - if (PageHuge(page)) > - page = compound_head(page); > - > - if (test_bit(PG_dcache_clean, &page->flags)) > - clear_bit(PG_dcache_clean, &page->flags); > + if (test_bit(PG_dcache_clean, &folio->flags)) > + clear_bit(PG_dcache_clean, &folio->flags); > } > +#define flush_dcache_folio flush_dcache_folio > #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 > > +static inline void flush_dcache_page(struct page *page) > +{ > + flush_dcache_folio(page_folio(page)); > +} > + > /* > * RISC-V doesn't have an instruction to flush parts of the instruction cache, > * so instead we just flush the whole thing. > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index b516f3b59616..3a3a776fc047 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -405,8 +405,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) > > > /* Commit new configuration to MMU hardware */ > -static inline void update_mmu_cache(struct vm_area_struct *vma, > - unsigned long address, pte_t *ptep) > +static inline void update_mmu_cache_range(struct vm_area_struct *vma, > + unsigned long address, pte_t *ptep, unsigned int nr) > { > /* > * The kernel assumes that TLBs don't cache invalid entries, but > @@ -415,8 +415,11 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, > * Relying on flush_tlb_fix_spurious_fault would suffice, but > * the extra traps reduce performance. So, eagerly SFENCE.VMA. > */ > - local_flush_tlb_page(address); > + while (nr--) > + local_flush_tlb_page(address + nr * PAGE_SIZE); > } > +#define update_mmu_cache(vma, addr, ptep) \ > + update_mmu_cache_range(vma, addr, ptep, 1) > > #define __HAVE_ARCH_UPDATE_MMU_TLB > #define update_mmu_tlb update_mmu_cache > @@ -456,12 +459,21 @@ static inline void __set_pte_at(struct mm_struct *mm, > set_pte(ptep, pteval); > } > > -static inline void set_pte_at(struct mm_struct *mm, > - unsigned long addr, pte_t *ptep, pte_t pteval) > +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > + pte_t *ptep, pte_t pteval, unsigned int nr) > { > - page_table_check_ptes_set(mm, addr, ptep, pteval, 1); > - __set_pte_at(mm, addr, ptep, pteval); > + page_table_check_ptes_set(mm, addr, ptep, pteval, nr); > + > + for (;;) { > + __set_pte_at(mm, addr, ptep, pteval); > + if (--nr == 0) > + break; > + ptep++; > + addr += PAGE_SIZE; > + pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; > + } > } > +#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) > > static inline void pte_clear(struct mm_struct *mm, > unsigned long addr, pte_t *ptep) > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > index fcd6145fbead..e36a851e5788 100644 > --- a/arch/riscv/mm/cacheflush.c > +++ b/arch/riscv/mm/cacheflush.c > @@ -81,16 +81,9 @@ void flush_icache_mm(struct mm_struct *mm, bool local) > #ifdef CONFIG_MMU > void flush_icache_pte(pte_t pte) > { > - struct page *page = pte_page(pte); > + struct folio *folio = page_folio(pte_page(pte)); > > - /* > - * HugeTLB pages are always fully mapped, so only setting head page's > - * PG_dcache_clean flag is enough. > - */ > - if (PageHuge(page)) > - page = compound_head(page); > - > - if (!test_bit(PG_dcache_clean, &page->flags)) { > + if (!test_bit(PG_dcache_clean, &folio->flags)) { > flush_icache_all(); > set_bit(PG_dcache_clean, &page->flags); > } Acked-by: Palmer Dabbelt