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Shutemov" To: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= Cc: "Kirill A. Shutemov" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Jonathan Corbet , Andy Lutomirski , Peter Zijlstra , Ard Biesheuvel , Jan Kiszka , Kieran Bingham , Michael Roth , Rick Edgecombe , Brijesh Singh , Sandipan Das , Tom Lendacky , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional Message-ID: References: <20250516091534.3414310-1-kirill.shutemov@linux.intel.com> <20250516091534.3414310-4-kirill.shutemov@linux.intel.com> <51d78ee7-4b68-425b-bccb-d123d7210305@suse.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Rspam-User: X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 6AF744000A X-Stat-Signature: 8ygtijt6aau5fi7ffphyqs3o4rtedzs6 X-HE-Tag: 1747396306-326651 X-HE-Meta: U2FsdGVkX1/1o9mF1ykhw4iWnxyOIyxbh7UNyyLoDoqMGEIExJd7jqLuTw2Q9id1cTihW6qcMYcmESw9A6GF1/Q11hZtEveF9ia1TEEChTgANQ8XG8ApbYGLtox3IicB3xP9YqrPmZYYugtXCxuOSAv1D8NPldH5GkvrQD9UW1lN56KrOQCZ9NN/TAMoRpiO3Pm59yMaKp3dJi6vAmMerOMIAq0Iix6RcK63yQngJDt/i0i+j6Nt9u+tIcSiGC1ELKYKkxRY1lcL8HfVhrWowdtfCfNk0YWV/H9dmZS4DWcYKJAX2q2wBok3JEyHDKb38f1mk6fQeDIU5eB3lO0+0HcrfBNoohunM/wq5Tw3/op7KmFI5HDLJGfC2rdIAggbQPjKUP+yPR8fWDzwa8ubDfjYOwqPpRRvxOl9dpmFlC4hWWM2COhy+yen4PRGqO93da4nR3Q3Tl1/KNgHvZLyufH3bodIgUkZk9xqRRX5m1T1Vw/ufRCyEp8X3k+AGWz3j37542DVOyzVJhSjhMMrsJGXDyLNaboggjmzbQMNE9/CcwnhIaUf/iLZHUADou23xbW14z6l1Yp3mnSsIA2xgBZHAu8rmwqxQBMp8b8L8qQYdxxjBpvy/tsUlykE1dHB8WNGl9jT+GRjEUU8IvmIQkRiHUpTI6P7yk3+ORcF7XdqeVk/c6y+pvuKUEbrCVWJRMz5EmRTSDE1bzT3MxXoamdSu9X7lUEVR8ZXhG5X7RxVKXIZphLR82oFQ8OXCHDLzA88mvh5Fjb/WyBw14jdmWM92UKhC6SHfV+o4Oh4LmP1PjPK7Zyxxafong52QxUPplWsauDJKsxTX901ryjljftroIuWJuGVMFxBmYBsbmOh/0JjsVhNeY9UvCWUcxkQ6KtCIpYiyMVwvqbebghtQaC8b80oc+HvS2Hmq2HoLAAAJPt4JQq+tj6tILyRNkj4v0M3lSkT9q65k/dZ+a7 42+yB/i0 SPIcpoP06nwJXt5lPGgq0HtqCNwkgif8tLfaarw3AdEC5YAG1YnfwDx2+RTfrp7dF61igDaUOdf3Leq6DN7i2PT4LWrySUvJoa2fUBzhJvz0F4YRIYB9OVDi4gHYSto6zkzx7XFzEobCtLWVZXevsksQ/1Dmx+vIeynlyrq4uBlbATJ/7F1Tos0huPt8Admx3gfE1+kIbXRBKapnZzZmuUMSGgVWAOKS5+D51xZlVCNb+JW8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Fri, May 16, 2025 at 02:47:46PM +0300, Kirill A. Shutemov wrote: > On Fri, May 16, 2025 at 01:29:27PM +0200, Jürgen Groß wrote: > > On 16.05.25 13:09, Kirill A. Shutemov wrote: > > > On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote: > > > > On 16.05.25 11:15, Kirill A. Shutemov wrote: > > > > > Both Intel and AMD CPUs support 5-level paging, which is expected to > > > > > become more widely adopted in the future. > > > > > > > > > > Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable. > > > > > > > > > > Signed-off-by: Kirill A. Shutemov > > > > > Suggested-by: Borislav Petkov > > > > > --- > > > > > Documentation/arch/x86/cpuinfo.rst | 8 +++---- > > > > > .../arch/x86/x86_64/5level-paging.rst | 9 -------- > > > > > arch/x86/Kconfig | 22 +------------------ > > > > > arch/x86/Kconfig.cpufeatures | 4 ---- > > > > > arch/x86/boot/compressed/pgtable_64.c | 11 ++-------- > > > > > arch/x86/boot/header.S | 4 ---- > > > > > arch/x86/boot/startup/map_kernel.c | 5 +---- > > > > > arch/x86/include/asm/page_64.h | 2 -- > > > > > arch/x86/include/asm/page_64_types.h | 7 ------ > > > > > arch/x86/include/asm/pgtable_64_types.h | 18 --------------- > > > > > arch/x86/kernel/alternative.c | 2 +- > > > > > arch/x86/kernel/head64.c | 2 -- > > > > > arch/x86/kernel/head_64.S | 2 -- > > > > > arch/x86/mm/init.c | 4 ---- > > > > > arch/x86/mm/pgtable.c | 2 +- > > > > > drivers/firmware/efi/libstub/x86-5lvl.c | 2 +- > > > > > 16 files changed, 10 insertions(+), 94 deletions(-) > > > > > > > > There are some instances of: > > > > > > > > #if CONFIG_PGTABLE_LEVELS >= 5 > > > > > > > > in 64-bit-only code under arch/x86, which could be simplified, too. > > > > > > > > They are still correct, but I wanted to hint at further code removals > > > > being possible. > > > > > > Okay, fair enough. Fixup is below. > > > > > > Did I miss anything else? > > > > Yes. > > > > One more instance in arch/x86/xen/mmu_pv.c, > > Ah. Right. > > > one in arch/x86/include/asm/paravirt.h, > > one in arch/x86/include/asm/paravirt_types.h, > > one in arch/x86/kernel/paravirt.c > > Hm. Is paravirt 64-bit only? Oh. It is PARAVIRT_XXL thingy which is only used by XEN_PV which is 64-bit only, right? Do we want to make PARAVIRT_XXL explicitly 64-bit only? -- Kiryl Shutsemau / Kirill A. Shutemov