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Shutemov" To: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= Cc: "Kirill A. Shutemov" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Jonathan Corbet , Andy Lutomirski , Peter Zijlstra , Ard Biesheuvel , Jan Kiszka , Kieran Bingham , Michael Roth , Rick Edgecombe , Brijesh Singh , Sandipan Das , Tom Lendacky , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional Message-ID: References: <20250516091534.3414310-1-kirill.shutemov@linux.intel.com> <20250516091534.3414310-4-kirill.shutemov@linux.intel.com> <51d78ee7-4b68-425b-bccb-d123d7210305@suse.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <51d78ee7-4b68-425b-bccb-d123d7210305@suse.com> X-Stat-Signature: hbedr9a74z7y4urqxzwg9fy8ex9fp6d5 X-Rspamd-Queue-Id: 7192C20002 X-Rspam-User: X-Rspamd-Server: rspam02 X-HE-Tag: 1747396075-241339 X-HE-Meta: U2FsdGVkX193OmIGxAhMdIxzFc8d3uvQO2Bc6uzaPXgoaMosb3u77ujK5uQdFTf5pu+CCqus257Tbw7SEuhk4tOJ41+PZ7rNPpYDlcRmQQEx8t+PoqNMYjYfUOykcUCnf08pq4CLfL4uPS5wRsFKMe42ioBj4BUUV7BOl2f8qMGtTfQmHgIeYUMS01GrbH65rL5+5ctN6eba2QBA4ZSR1PI2sE5dYYtwoZx9H9MtJCKsbQy3tfSCn7N3NK2/9r0Yc5JKfEdelmp3ssJHUjlyu4xt5OTcqynWpmWwHJl6C2XObgoYI7Oreb8+/S5iXkz+rCWdPPtejXPhCoW4Bv7P0g2tmZn9mWIlMlaQ1i0GZgx0hgMZdy8nbfZ9mGcMMO3RCUVjyGLmYGU2O16GyRtwtBisEkJr1/c5spwKN7h6lpB433x6xBp2wo5YLoqjJXr8oJXm7etuteoNQOFikM+i+XRSxTgr2GLmUqS0+mt1SdBr4s8CgUrauvsIgaS00NwW1lw2940jPO9clE6AgUbXCFQIPcXh3f6L6EYa3ndPYPe2uibaFVXCdBVt6KXdRHNuUFA+0UNkEZi8ELoSIUeTrdRAowasLwFElQsWRUO4cNj5yecSsdAN6g7FT/mkoUBdkz+LID/6yQGb42Q2UA+cQXqwQovjx4V44Pvk+sl9V54DmIV5DpsfbPk0/SRdPl1glpg4XcSL16h8mxIQkaxJMR68LJT5nMOdBjTVaS4UYs6lsVrEzbx9fPCqvnjrrG8XLA8SRXczZv2itq1vEfY0USrOv7nuchiExa1hJl5u47JxR9M+zmURe3KiTGKB6qU13Xcn87tByuQPYPsGgg6YLq3osNs430aqK1RCrGqJkx36USsRwl4xrvVksrFRzykBbOhfvDwS710vqa6bfPBhZDGzUj3bSpfRGo14XDjZ5QA48KKLt0DEXdQDa7jBqgWIIb+dCawBc7xNj2UTWJ/ l3TGUeXX 89HjJDGZTLeXTAR08G9lQfaOviyMdkb3542f28R0ebYABxXA0iOpdAZmJehu2StBMrL0pjyvfskMgWlrgOPI0mE8BAYunXWkwXKHL1v6+tgH10h0RtMGJdYvAcfe6y26biXlk4D4WG5j+OQpgGu+lTHoCH3MNtUS3QjNs11M3wQn6nREqhZjW/O0IR/Qn2XDlPTm/XI5SVCZg9FBowsuisyYdwJV1Un4IFbQ0yf785PK3hr8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Fri, May 16, 2025 at 01:29:27PM +0200, Jürgen Groß wrote: > On 16.05.25 13:09, Kirill A. Shutemov wrote: > > On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote: > > > On 16.05.25 11:15, Kirill A. Shutemov wrote: > > > > Both Intel and AMD CPUs support 5-level paging, which is expected to > > > > become more widely adopted in the future. > > > > > > > > Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable. > > > > > > > > Signed-off-by: Kirill A. Shutemov > > > > Suggested-by: Borislav Petkov > > > > --- > > > > Documentation/arch/x86/cpuinfo.rst | 8 +++---- > > > > .../arch/x86/x86_64/5level-paging.rst | 9 -------- > > > > arch/x86/Kconfig | 22 +------------------ > > > > arch/x86/Kconfig.cpufeatures | 4 ---- > > > > arch/x86/boot/compressed/pgtable_64.c | 11 ++-------- > > > > arch/x86/boot/header.S | 4 ---- > > > > arch/x86/boot/startup/map_kernel.c | 5 +---- > > > > arch/x86/include/asm/page_64.h | 2 -- > > > > arch/x86/include/asm/page_64_types.h | 7 ------ > > > > arch/x86/include/asm/pgtable_64_types.h | 18 --------------- > > > > arch/x86/kernel/alternative.c | 2 +- > > > > arch/x86/kernel/head64.c | 2 -- > > > > arch/x86/kernel/head_64.S | 2 -- > > > > arch/x86/mm/init.c | 4 ---- > > > > arch/x86/mm/pgtable.c | 2 +- > > > > drivers/firmware/efi/libstub/x86-5lvl.c | 2 +- > > > > 16 files changed, 10 insertions(+), 94 deletions(-) > > > > > > There are some instances of: > > > > > > #if CONFIG_PGTABLE_LEVELS >= 5 > > > > > > in 64-bit-only code under arch/x86, which could be simplified, too. > > > > > > They are still correct, but I wanted to hint at further code removals > > > being possible. > > > > Okay, fair enough. Fixup is below. > > > > Did I miss anything else? > > Yes. > > One more instance in arch/x86/xen/mmu_pv.c, Ah. Right. > one in arch/x86/include/asm/paravirt.h, > one in arch/x86/include/asm/paravirt_types.h, > one in arch/x86/kernel/paravirt.c Hm. Is paravirt 64-bit only? -- Kiryl Shutsemau / Kirill A. Shutemov