Re: [PATCH -next v2 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto

From: <Conor.Dooley@microchip.com>
To: <i@zenithal.me>, <palmer@rivosinc.com>,
	<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
	<heiko@sntech.de>
Cc: <atishp@rivosinc.com>, <anup@brainfault.org>,
	<ebiederm@xmission.com>, <keescook@chromium.org>,
	<linux-mm@kvack.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-api@vger.kernel.org>,
	<mtk.manpages@gmail.com>, <linux-man@vger.kernel.org>,
	<jiatai2021@iscas.ac.cn>
Subject: Re: [PATCH -next v2 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto
Date: Wed, 18 May 2022 09:39:53 +0000	[thread overview]
Message-ID: <fba8ab6e-17bf-1fe1-ad5f-339276907298@microchip.com> (raw)
In-Reply-To: <YoS7lgTmcRT0q9y+@Sun>

On 18/05/2022 10:25, Hongren (Zenithal) Zheng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> userspace currently lacks a way to detect whether the
> platform has Bitmanip/Scalar Crypto capability,
> this commit provides a way such that the userspace
> can detect it.
> 
> RISC-V currently still has no mature mechanism,
> but no matter how things in the spec changes,
> (no matter how "M" mode things change), the kernel
> still needs to offer some API to the userspace.
> 
> More discussion can be found at
> https://github.com/openssl/openssl/pull/18197
> Userspace currently has to use env var to detect them.
> 
> This commit along does not assume any specific mechanism
> below kernel.

s/along/alone?

But I think you could rewrite this sentence to make it
clearer, I had to read it more than once to see if that was
actually a typo or not.
Possibly swap "This commit" for "This interface" or similar,
both here and in the first paragraph.
Maybe something like:

"This interface does not make any assumptions about the
underlying hardware"

Thanks,
Conor.

> 
> Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
> ---
>   arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
> index 46dc3f5ee99f..bfed3e5c338c 100644
> --- a/arch/riscv/include/uapi/asm/hwcap.h
> +++ b/arch/riscv/include/uapi/asm/hwcap.h
> @@ -22,4 +22,26 @@
>   #define COMPAT_HWCAP_ISA_D     (1 << ('D' - 'A'))
>   #define COMPAT_HWCAP_ISA_C     (1 << ('C' - 'A'))
> 
> +/*
> + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
> + *
> + * As only 32 bits of elf_hwcap (in kernel) could be used
> + * and RISC-V has reserved 26 bits of it, other caps like
> + * bitmanip and crypto can not be placed in AT_HWCAP
> + */
> +#define COMPAT_HWCAP2_ISA_ZBA   (1 <<  0)
> +#define COMPAT_HWCAP2_ISA_ZBB   (1 <<  1)
> +#define COMPAT_HWCAP2_ISA_ZBC   (1 <<  2)
> +#define COMPAT_HWCAP2_ISA_ZBS   (1 <<  3)
> +#define COMPAT_HWCAP2_ISA_ZBKB  (1 <<  4)
> +#define COMPAT_HWCAP2_ISA_ZBKC  (1 <<  5)
> +#define COMPAT_HWCAP2_ISA_ZBKX  (1 <<  6)
> +#define COMPAT_HWCAP2_ISA_ZKND  (1 <<  7)
> +#define COMPAT_HWCAP2_ISA_ZKNE  (1 <<  8)
> +#define COMPAT_HWCAP2_ISA_ZKNH  (1 <<  9)
> +#define COMPAT_HWCAP2_ISA_ZKSED (1 << 10)
> +#define COMPAT_HWCAP2_ISA_ZKSH  (1 << 11)
> +#define COMPAT_HWCAP2_ISA_ZKR   (1 << 12)
> +#define COMPAT_HWCAP2_ISA_ZKT   (1 << 13)
> +
>   #endif /* _UAPI_ASM_RISCV_HWCAP_H */
> --
> 2.35.1
> 
> 
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