From: Shiju Jose <shiju.jose@huawei.com>
To: fan <nifan.cxl@gmail.com>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
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Linuxarm <linuxarm@huawei.com>
Subject: RE: [RFC PATCH v9 01/11] EDAC: Add generic EDAC RAS feature driver
Date: Wed, 17 Jul 2024 11:06:42 +0000 [thread overview]
Message-ID: <f271f9a257e64b398783717237e63186@huawei.com> (raw)
In-Reply-To: <Zpa1UNTOcJgcq2q5@debian>
Hi Fan,
Thanks for the feedback.
>-----Original Message-----
>From: fan <nifan.cxl@gmail.com>
>Sent: 16 July 2024 19:01
>To: Shiju Jose <shiju.jose@huawei.com>
>Cc: linux-edac@vger.kernel.org; linux-cxl@vger.kernel.org; linux-
>acpi@vger.kernel.org; linux-mm@kvack.org; linux-kernel@vger.kernel.org;
>bp@alien8.de; tony.luck@intel.com; rafael@kernel.org; lenb@kernel.org;
>mchehab@kernel.org; dan.j.williams@intel.com; dave@stgolabs.net; Jonathan
>Cameron <jonathan.cameron@huawei.com>; dave.jiang@intel.com;
>alison.schofield@intel.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>david@redhat.com; Vilas.Sridharan@amd.com; leo.duran@amd.com;
>Yazen.Ghannam@amd.com; rientjes@google.com; jiaqiyan@google.com;
>Jon.Grimm@amd.com; dave.hansen@linux.intel.com;
>naoya.horiguchi@nec.com; james.morse@arm.com; jthoughton@google.com;
>somasundaram.a@hpe.com; erdemaktas@google.com; pgonda@google.com;
>duenwen@google.com; mike.malvestuto@intel.com; gthelen@google.com;
>wschwartz@amperecomputing.com; dferguson@amperecomputing.com;
>wbs@os.amperecomputing.com; nifan.cxl@gmail.com; tanxiaofei
><tanxiaofei@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>; Roberto
>Sassu <roberto.sassu@huawei.com>; kangkang.shen@futurewei.com;
>wanghuiqiang <wanghuiqiang@huawei.com>; Linuxarm
><linuxarm@huawei.com>
>Subject: Re: [RFC PATCH v9 01/11] EDAC: Add generic EDAC RAS feature driver
>
>On Tue, Jul 16, 2024 at 04:03:25PM +0100, shiju.jose@huawei.com wrote:
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>> Add generic EDAC driver supports registering RAS features supported in
>> the system. The driver exposes feature's control attributes to the
>> userspace in /sys/bus/edac/devices/<dev-name>/<ras-feature>/
>>
>> Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>> ---
>> drivers/edac/Makefile | 1 +
>> drivers/edac/edac_ras_feature.c | 155
>> +++++++++++++++++++++++++++++++ include/linux/edac_ras_feature.h |
>> 66 +++++++++++++
>> 3 files changed, 222 insertions(+)
>> create mode 100755 drivers/edac/edac_ras_feature.c create mode
>> 100755 include/linux/edac_ras_feature.h
>>
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index
>> 9c09893695b7..c532b57a6d8a 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -10,6 +10,7 @@ obj-$(CONFIG_EDAC) := edac_core.o
>>
>> edac_core-y := edac_mc.o edac_device.o edac_mc_sysfs.o
>> edac_core-y += edac_module.o edac_device_sysfs.o wq.o
>> +edac_core-y += edac_ras_feature.o
>>
>> edac_core-$(CONFIG_EDAC_DEBUG) += debugfs.o
>>
>> diff --git a/drivers/edac/edac_ras_feature.c
>> b/drivers/edac/edac_ras_feature.c new file mode 100755 index
>> 000000000000..24a729fea66f
>> --- /dev/null
>> +++ b/drivers/edac/edac_ras_feature.c
>> @@ -0,0 +1,155 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * EDAC RAS control feature driver supports registering RAS
>> + * features with the EDAC and exposes the feature's control
>> + * attributes to the userspace in sysfs.
>> + *
>> + * Copyright (c) 2024 HiSilicon Limited.
>> + */
>> +
>> +#define pr_fmt(fmt) "EDAC RAS CONTROL FEAT: " fmt
>> +
>> +#include <linux/edac_ras_feature.h>
>> +
>> +static void edac_ras_dev_release(struct device *dev) {
>> + struct edac_ras_feat_ctx *ctx =
>> + container_of(dev, struct edac_ras_feat_ctx, dev);
>> +
>> + kfree(ctx);
>> +}
>> +
>> +const struct device_type edac_ras_dev_type = {
>> + .name = "edac_ras_dev",
>> + .release = edac_ras_dev_release,
>> +};
>> +
>> +static void edac_ras_dev_unreg(void *data) {
>> + device_unregister(data);
>> +}
>> +
>> +static int edac_ras_feat_scrub_init(struct device *parent,
>> + struct edac_scrub_data *sdata,
>> + const struct edac_ras_feature *sfeat,
>> + const struct attribute_group **attr_groups) {
>> + sdata->ops = sfeat->scrub_ops;
>> + sdata->private = sfeat->scrub_ctx;
>> +
>> + return 1;
>> +}
>> +
>> +static int edac_ras_feat_ecs_init(struct device *parent,
>> + struct edac_ecs_data *edata,
>> + const struct edac_ras_feature *efeat,
>> + const struct attribute_group **attr_groups) {
>> + int num = efeat->ecs_info.num_media_frus;
>> +
>> + edata->ops = efeat->ecs_ops;
>> + edata->private = efeat->ecs_ctx;
>> +
>> + return num;
>> +}
>> +
>> +/**
>> + * edac_ras_dev_register - register device for ras features with edac
>> + * @parent: client device.
>> + * @name: client device's name.
>> + * @private: parent driver's data to store in the context if any.
>> + * @num_features: number of ras features to register.
>> + * @ras_features: list of ras features to register.
>> + *
>> + * Returns 0 on success, error otherwise.
>> + * The new edac_ras_feat_ctx would be freed automatically.
>> + */
>> +int edac_ras_dev_register(struct device *parent, char *name,
>> + void *private, int num_features,
>> + const struct edac_ras_feature *ras_features) {
>> + const struct attribute_group **ras_attr_groups;
>> + struct edac_ras_feat_ctx *ctx;
>> + int attr_gcnt = 0;
>> + int ret, feat;
>> +
>> + if (!parent || !name || !num_features || !ras_features)
>> + return -EINVAL;
>> +
>> + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
>> + if (!ctx)
>> + return -ENOMEM;
>> +
>> + ctx->dev.parent = parent;
>> + ctx->private = private;
>> +
>> + /* Double parse so we can make space for attributes */
>> + for (feat = 0; feat < num_features; feat++) {
>> + switch (ras_features[feat].feat) {
>> + case ras_feat_scrub:
>> + attr_gcnt++;
>> + break;
>> + case ras_feat_ecs:
>> + attr_gcnt +=
>ras_features[feat].ecs_info.num_media_frus;
>> + break;
>> + default:
>> + ret = -EINVAL;
>> + goto ctx_free;
>> + }
>> + }
>> +
>> + ras_attr_groups = devm_kzalloc(parent,
>> + (attr_gcnt + 1) * sizeof(*ras_attr_groups),
>> + GFP_KERNEL);
>> + if (!ras_attr_groups) {
>> + ret = -ENOMEM;
>> + goto ctx_free;
>> + }
>> +
>> + attr_gcnt = 0;
>> + for (feat = 0; feat < num_features; feat++, ras_features++) {
>> + if (ras_features->feat == ras_feat_scrub) {
>> + if (!ras_features->scrub_ops)
>> + continue;
>> + ret = edac_ras_feat_scrub_init(parent, &ctx->scrub,
>> + ras_features,
>&ras_attr_groups[attr_gcnt]);
>> + if (ret < 0)
>> + goto ctx_free;
>> +
>> + attr_gcnt += ret;
>> + } else if (ras_features->feat == ras_feat_ecs) {
>> + if (!ras_features->ecs_ops)
>> + continue;
>> + ret = edac_ras_feat_ecs_init(parent, &ctx->ecs,
>> + ras_features,
>&ras_attr_groups[attr_gcnt]);
>> + if (ret < 0)
>> + goto ctx_free;
>> +
>> + attr_gcnt += ret;
>> + } else {
>> + ret = -EINVAL;
>> + goto ctx_free;
>We already check this in the first pass, cannot be reached in the second pass.
Will change.
>> + }
>Why use if/else instead of using switch/case as above?
Will do.
>> + }
>> + ras_attr_groups[attr_gcnt] = NULL;
>> + ctx->dev.bus = edac_get_sysfs_subsys();
>> + ctx->dev.type = &edac_ras_dev_type;
>> + ctx->dev.groups = ras_attr_groups;
>> + dev_set_drvdata(&ctx->dev, ctx);
>> + ret = dev_set_name(&ctx->dev, name);
>> + if (ret)
>> + goto ctx_free;
>> +
>> + ret = device_register(&ctx->dev);
>> + if (ret) {
>> + put_device(&ctx->dev);
>need to free ctx?
Will fix.
>> + return ret;
>> + }
>> +
>> + return devm_add_action_or_reset(parent, edac_ras_dev_unreg,
>> +&ctx->dev);
>> +
>> +ctx_free:
>> + kfree(ctx);
>> + return ret;
>> +}
>> +EXPORT_SYMBOL_GPL(edac_ras_dev_register);
>> diff --git a/include/linux/edac_ras_feature.h
>> b/include/linux/edac_ras_feature.h
>> new file mode 100755
>> index 000000000000..000e99141023
>> --- /dev/null
>> +++ b/include/linux/edac_ras_feature.h
>> @@ -0,0 +1,66 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * EDAC RAS control features.
>> + *
>> + * Copyright (c) 2024 HiSilicon Limited.
>> + */
>> +
>> +#ifndef __EDAC_RAS_FEAT_H
>> +#define __EDAC_RAS_FEAT_H
>> +
>> +#include <linux/types.h>
>> +#include <linux/edac.h>
>> +
>> +#define EDAC_RAS_NAME_LEN 128
>> +
>> +enum edac_ras_feat {
>> + ras_feat_scrub,
>> + ras_feat_ecs,
>> + ras_feat_max
>> +};
>Use uppercase for the strings.
Will do.
>
>Fan
>> +
>> +struct edac_ecs_ex_info {
>> + u16 num_media_frus;
>> +};
>> +
>> +/*
>> + * EDAC RAS feature information structure */ struct edac_scrub_data
>> +{
>> + const struct edac_scrub_ops *ops;
>> + void *private;
>> +};
>> +
>> +struct edac_ecs_data {
>> + const struct edac_ecs_ops *ops;
>> + void *private;
>> +};
>> +
>> +struct device;
>> +
>> +struct edac_ras_feat_ctx {
>> + struct device dev;
>> + void *private;
>> + struct edac_scrub_data scrub;
>> + struct edac_ecs_data ecs;
>> +};
>> +
>> +struct edac_ras_feature {
>> + enum edac_ras_feat feat;
>> + union {
>> + const struct edac_scrub_ops *scrub_ops;
>> + const struct edac_ecs_ops *ecs_ops;
>> + };
>> + union {
>> + struct edac_ecs_ex_info ecs_info;
>> + };
>> + union {
>> + void *scrub_ctx;
>> + void *ecs_ctx;
>> + };
>> +};
>> +
>> +int edac_ras_dev_register(struct device *parent, char *dev_name,
>> + void *parent_pvt_data, int num_features,
>> + const struct edac_ras_feature *ras_features); #endif
>/*
>> +__EDAC_RAS_FEAT_H */
>> --
>> 2.34.1
>>
Thanks,
Shiju
next prev parent reply other threads:[~2024-07-17 11:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-16 15:03 [RFC PATCH v9 00/11] EDAC: Scrub: Introduce generic EDAC RAS control feature driver + CXL/ACPI-RAS2 drivers shiju.jose
2024-07-16 15:03 ` [RFC PATCH v9 01/11] EDAC: Add generic EDAC RAS feature driver shiju.jose
2024-07-16 18:00 ` fan
2024-07-17 11:06 ` Shiju Jose [this message]
2024-07-17 10:00 ` Mauro Carvalho Chehab
2024-07-17 11:01 ` Shiju Jose
2024-07-18 6:19 ` Mauro Carvalho Chehab
2024-07-16 15:03 ` [RFC PATCH v9 02/11] EDAC: Add EDAC scrub control driver shiju.jose
2024-07-17 12:56 ` Mauro Carvalho Chehab
2024-07-17 14:07 ` Shiju Jose
2024-07-18 7:03 ` Mauro Carvalho Chehab
2024-07-16 15:03 ` [RFC PATCH v9 03/11] EDAC: Add EDAC ECS " shiju.jose
2024-07-17 13:08 ` Mauro Carvalho Chehab
2024-07-17 17:13 ` nifan.cxl
2024-07-16 15:03 ` [RFC PATCH v9 04/11] cxl/mbox: Add GET_SUPPORTED_FEATURES mailbox command shiju.jose
2024-07-17 17:28 ` nifan.cxl
2024-07-16 15:03 ` [RFC PATCH v9 05/11] cxl/mbox: Add GET_FEATURE " shiju.jose
2024-07-17 18:08 ` nifan.cxl
2024-07-18 9:11 ` Shiju Jose
2024-07-16 15:03 ` [RFC PATCH v9 06/11] cxl/mbox: Add SET_FEATURE " shiju.jose
2024-07-17 20:13 ` nifan.cxl
2024-07-18 9:15 ` Shiju Jose
2024-07-16 15:03 ` [RFC PATCH v9 07/11] cxl/memscrub: Add CXL memory device patrol scrub control feature shiju.jose
2024-07-18 22:02 ` fan
2024-07-16 15:03 ` [RFC PATCH v9 08/11] cxl/memscrub: Add CXL memory device ECS " shiju.jose
2024-07-19 18:43 ` fan
2024-07-24 9:10 ` Shiju Jose
2024-07-16 15:03 ` [RFC PATCH v9 09/11] platform: Add __free() based cleanup function for platform_device_put shiju.jose
2024-07-16 15:03 ` [RFC PATCH v9 10/11] ACPI:RAS2: Add ACPI RAS2 driver shiju.jose
2024-07-16 15:03 ` [RFC PATCH v9 11/11] ras: scrub: ACPI RAS2: Add memory " shiju.jose
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