From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36421C38A02 for ; Sun, 30 Oct 2022 13:19:27 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 486676B0071; Sun, 30 Oct 2022 09:19:26 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 4406A6B0073; Sun, 30 Oct 2022 09:19:26 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 325118E0001; Sun, 30 Oct 2022 09:19:26 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 231906B0071 for ; Sun, 30 Oct 2022 09:19:26 -0400 (EDT) Received: from smtpin08.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id E4949AAFB9 for ; Sun, 30 Oct 2022 13:19:25 +0000 (UTC) X-FDA: 80077672290.08.075ED35 Received: from gentwo.de (gentwo.de [161.97.139.209]) by imf07.hostedemail.com (Postfix) with ESMTP id 2C9504000C for ; Sun, 30 Oct 2022 13:19:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gentwo.de; s=default; t=1667135962; bh=7ZB8QhocN2s3hPoZ/1bKqbKsfF0/49Hms0o4+0l6fFc=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=FJRwjXgF1aJxSRirzjcSCeGAYHYxhTCdgxhQP+kVRDy0d7hWm3nSp63mBkgXq96+8 iGq1Wjed2murfyBGX0nw14/IK1PoRaTBaivR3dQ4M/rlEkIs1JOSbOLDbTrlO10bFa GrMLlrvXU4X2Y0jDFMbkukp0zNbls+4uu8U767nktHE7nLDq0LDf+5EQ+0vb7tmRVN a7tAga2rL2KS1v0GR+6LF/aFYfMNW9R5RIOZTr7F+w73/Cm2iBmyICjrWIkBfJoyZ7 aKyhmzQ2UE5XzWw8qkh+mNBogZel2JsmjEn/ZfXaAEzRzUtSbR0nNwCo012/cBC8uL jdX1mwR1vE58g== Received: by gentwo.de (Postfix, from userid 1001) id C310CB001C0; Sun, 30 Oct 2022 14:19:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by gentwo.de (Postfix) with ESMTP id BF90AB000A7; Sun, 30 Oct 2022 14:19:22 +0100 (CET) Date: Sun, 30 Oct 2022 14:19:22 +0100 (CET) From: Christoph Lameter To: Wen Yao cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, dennis@kernel.org, tj@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCH 1/2] riscv: percpu:Add riscv percpu operations In-Reply-To: <20221026104015.565468-2-haiwenyao@uniontech.com> Message-ID: References: <20221026104015.565468-1-haiwenyao@uniontech.com> <20221026104015.565468-2-haiwenyao@uniontech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII ARC-Authentication-Results: i=1; imf07.hostedemail.com; dkim=none ("invalid DKIM record") header.d=gentwo.de header.s=default header.b=FJRwjXgF; dmarc=pass (policy=none) header.from=gentwo.de; spf=pass (imf07.hostedemail.com: domain of cl@gentwo.de designates 161.97.139.209 as permitted sender) smtp.mailfrom=cl@gentwo.de ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1667135965; a=rsa-sha256; cv=none; b=BzhOUBb1tFh5WR1rV6VhIDuMUWetB2uisOY0EuoPEZXDI3hg5wXoi06VkDkqIxOFW7SyEg jASgnXHQfWdgplwK43wl7bHCz70cf8+eHAYe7eGGAq2XyL/mF075Qjydn6Bmwx2EzkMytB F6yN3uqalu2iGEgbbCy/k/pzRpUgMmc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1667135965; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=A75M4V6jttisU2YpLkW9gAzlm0E6YJMgBVwsJda2dzE=; b=3HxJr+75iYWHJOuMuYb0IS2bSiDXW/EB0RQIjGKOS/iLlQ0a9SmGpSndgjGPp3rjyjumX4 d2uSwz1xvD6/fVWDLun1xoEoq7sTW3iLGCPzV0LtkDIv6vE7BNUEG8GMksF/gXeeo+ocVM os7QxS7YKiY2q3oAj0gNndL91UmAIkw= Authentication-Results: imf07.hostedemail.com; dkim=none ("invalid DKIM record") header.d=gentwo.de header.s=default header.b=FJRwjXgF; dmarc=pass (policy=none) header.from=gentwo.de; spf=pass (imf07.hostedemail.com: domain of cl@gentwo.de designates 161.97.139.209 as permitted sender) smtp.mailfrom=cl@gentwo.de X-Rspam-User: X-Stat-Signature: ppkr34twb4pp3td9xyf9u7394t51wd17 X-Rspamd-Queue-Id: 2C9504000C X-Rspamd-Server: rspam11 X-HE-Tag: 1667135964-132049 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, 26 Oct 2022, Wen Yao wrote: > This patch use riscv AMO(Atomic Memory Operation) instructions to > optimise some this_cpu_and this_cpu_or this_cpu_add operations. > It reuse cmpxchg_local() to impletment this_cpu_cmpxchg macros. > It reuse xchg_relaxed() to impletment this_cpu_xchg macros. Are you sure that these changes gives you any benefit vs disabling preempt or irq offs? I dont know too much about atomics on riscv but it looks like you are using full atomics. The performance penalty for the use of those is usually drastic. Often irq/preempt off is better. Could you run some of the synthetic tests to establish the benefit? F.e. run the synthetic tests for the slub allcator with and without these patches. > + __asm__ __volatile__( \ > + "amo" #asm_op ".w" \ amo = atomic operation?