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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2024 23:45:26.7132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 450f8b78-b3d9-4e25-0664-08dc37ee2c95 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9134 X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 03880140010 X-Stat-Signature: ep3jieosdge4xxn1q83mtzgyr948bzq6 X-HE-Tag: 1709077529-791851 X-HE-Meta: U2FsdGVkX19heg+pbwK5Yo2LQf4ZLhcFqrqjXcdGHXxkxEeNtlDtC2LZRB0txAL4C/AF/8PcL2f/2gLKbs+tFvrcxEDbv7RCbtpwKOS30ULtFvh0iBiXwPhHocFc9Kf+UKW1cncshBmeviOtf1uP0BHysvY3M4npnyt4RUxR2RusJxFMpqMT+vyk4V7cYmTm0w1BE8YFRelroPCMF0/XsZ4tSmInXwdGY9RWwCrmBFG1IVpMFeovF45BqGAcaTweDxUPDQNzXtZKLOL36JvAvG1FdSIm2RbOGYLEb3a6Cj/vLzclxIP64EszH+Sf4197vRE/SU6aTcOnh9PU1tCCl3HiUdjg2ZzDFW8CPqo9i63bz1/UZONK+paglbWMQprqzNYI4QrGA1VC24SuUF9xc63S1XLIEvzQO4yHKwC19/R8uqFMYD7coXnxlluSSDyJYG/TV+h0upxYKVbfBldqrnsyfsHK87EoKBnFO7vlMPY+cfkv9MbG/jT/iGPJvBdEKj1CfagP9YDyxowePrcF8JbR/3sZmvkp7cjkMi7bpoAJwU8ZQ+5Wzh8nQFkh6//yO6OGdFLHH/fo8vjfRTsjG5NKvSgrdRYboQoW18BMz0xQM6fYYC3+Aukl96NHUSfrWsDaFEKagKjOynaAUTGPXijJJ3sZZbbi5Zg0q/uyTstRkIk/4T3iZGBd9hSamSri+zN6N4TOLhPM37ndjtU2dfJofYoQ3XbXL52LzS0Z8d8k107wh6bU39/gM5Cvbtmoe8dwU3watu6v7mlICfEiGxiwEOgIK0ts8BpFxeK6XF3oVDzukze/D37ILzlxboi7ztnF07cklDf4xxPkn2UYnE+XN7JsTl3+Utj8otnEeW75QSnb8XUniUiHMW8bBpPT+zjIrCNjGRS1o/89C06bVgW+TuBvQYLWRYe5zRnPo/uJ07ILZH4Xw/910p5jFRIEr0Ri9SFmLJ5aqrXmzPM CNm6+SKI Be57i6DDLoDK/WilIS3JuhvFJlFGTYGkRlAUtf1//bGx8i1U= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 2/26/24 04:03, Ryan Roberts wrote: Hi Ryan! > Make clear the atmicity/consistency requirements of the API and how we "atomicity" > achieve them. > > Link: https://lore.kernel.org/linux-mm/Zc-Tqqfksho3BHmU@arm.com/ > Signed-off-by: Ryan Roberts > --- > arch/arm64/mm/contpte.c | 24 ++++++++++++++---------- > 1 file changed, 14 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/mm/contpte.c b/arch/arm64/mm/contpte.c > index be0a226c4ff9..1b64b4c3f8bf 100644 > --- a/arch/arm64/mm/contpte.c > +++ b/arch/arm64/mm/contpte.c > @@ -183,16 +183,20 @@ EXPORT_SYMBOL_GPL(contpte_ptep_get); > pte_t contpte_ptep_get_lockless(pte_t *orig_ptep) > { > /* > - * Gather access/dirty bits, which may be populated in any of the ptes > - * of the contig range. We may not be holding the PTL, so any contiguous > - * range may be unfolded/modified/refolded under our feet. Therefore we > - * ensure we read a _consistent_ contpte range by checking that all ptes > - * in the range are valid and have CONT_PTE set, that all pfns are > - * contiguous and that all pgprots are the same (ignoring access/dirty). > - * If we find a pte that is not consistent, then we must be racing with > - * an update so start again. If the target pte does not have CONT_PTE > - * set then that is considered consistent on its own because it is not > - * part of a contpte range. > + * The ptep_get_lockless() API requires us to read and return *orig_ptep > + * so that it is self-consistent, without the PTL held, so we may be > + * racing with other threads modifying the pte. Usually a READ_ONCE() > + * would suffice, but for the contpte case, we also need to gather the > + * access and dirty bits from across all ptes in the contiguous block, > + * and we can't read all of those neighbouring ptes atomically, so any This still leaves a key detail unexplained: how the accessed and dirty bits are handled. The above raises the *problem*, but then talks about getting a consistent set of reads. But during those consistent reads, the HW could have dirtied or read a page. And this code here is only returning a single pte. So I'm still feeling vague about what we're trying to say about accessed and dirty bits. > + * contiguous range may be unfolded/modified/refolded under our feet. > + * Therefore we ensure we read a _consistent_ contpte range by checking > + * that all ptes in the range are valid and have CONT_PTE set, that all > + * pfns are contiguous and that all pgprots are the same (ignoring > + * access/dirty). If we find a pte that is not consistent, then we must > + * be racing with an update so start again. If the target pte does not > + * have CONT_PTE set then that is considered consistent on its own > + * because it is not part of a contpte range. > */ > > pgprot_t orig_prot; thanks, -- John Hubbard NVIDIA