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Wed, 8 May 2024 14:26:24 -0400 (EDT) Received: from SSI-EX3.ssi.samsung.com (105.128.2.228) by SSI-EX1.ssi.samsung.com (105.128.2.226) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2507.35; Wed, 8 May 2024 11:26:23 -0700 Received: from SSI-EX3.ssi.samsung.com ([105.128.5.228]) by SSI-EX3.ssi.samsung.com ([105.128.5.228]) with mapi id 15.01.2507.035; Wed, 8 May 2024 11:26:23 -0700 From: Adam Manzanares To: Dan Williams CC: "lsf-pc@lists.linux-foundation.org" , "jonathan.cameron@huawei.com" , "dave@stgolabs.net" , Fan Ni , "dave.jiang@intel.com" , "ira.weiny@intel.com" , "alison.schofield@intel.com" , "vishal.l.verma@intel.com" , "gourry.memverge@gmail.com" , "wj28.lee@gmail.com" , "rientjes@google.com" , "ruansy.fnst@fujitsu.com" , "shradha.t@samsung.com" , "mcgrof@kernel.org" , Jim Harris , "mhocko@suse.com" , "linux-mm@kvack.org" , "linux-cxl@vger.kernel.org" , "linux-pci@vger.kernel.org" Subject: Re: [LSF/MM/BPF TOPIC] CXL Development Discussions Thread-Topic: [LSF/MM/BPF TOPIC] CXL Development Discussions Thread-Index: AQHan+tkd4BPRAK+n02hrtqAe44hSbGLVQ6AgALK6YA= Date: Wed, 8 May 2024 18:26:23 +0000 Message-ID: In-Reply-To: <66396c1938726_2f63a29443@dwillia2-mobl3.amr.corp.intel.com.notmuch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [105.128.2.176] Content-Type: text/plain; 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NP, its been great working together in the community. >=20 > > The first topic I believe we should discuss is how we can ensure as a g= roup > > that we are prioritizing upstream work. On a recent upstream CXL develo= pment > > discussion call there was a call to review more work. I apologize for n= ot > > grabbing the link, but I believe Dave Jiang is leveraging patchwork and= this > > link should be shared with others so we can help get more reviews where= needed. >=20 > Dave already replied here but one thing I will add is help keeping an > eye out for things that should be in queue. Likely a good way to > do that is send a note along with a review so both get reflected in the > tracking. >=20 Noted. > > The second topic I would like to discuss is how we integrate RAS featur= es that > > have similar equivalents in the kernel. A CXL device can provide info a= bout=20 > > memory media errors in a similar fashion to memory controllers that hav= e EDAC > > support. Discussions have been put on the list and I would like to hear= thoughts > > from the community about where this should go [1]. On the same topic CX= L has=20 > > port level RAS features and the PCIe DW series touched on this issue [= 2] >=20 > If I could uplevel this a bit there are multiple efforts in memory RAS > that likely want to figure out a cohesive story, or at least make > conscious decisions about implementation divergence. Some related work > that caught my eye: >=20 > * AMD M1300 specific poison handling that sounds similar to CXL List > Poison facility: > http://lore.kernel.org/r/20240214033516.1344948-3-yazen.ghannam@amd.com >=20 > * Scrub subsystem that has both ACPI and CXL intercepts: > http://lore.kernel.org/r/20240419164720.1765-1-shiju.jose@huawei.com >=20 > * Inconsistencies between firmware reported fatal errors and native > error handling, compare: >=20 > ghes_proc():: > if (ghes_severity(estatus->error_severity) >=3D GHES_SEV_PANIC) > __ghes_panic(ghes, estatus, buf_paddr, FIX_APEI_GHES_IRQ)= ; >=20 > ...vs: >=20 > pcie_do_recovery():: > /* TODO: Should kernel panic here? */ > pci_info(bridge, "device recovery failed\n"); >=20 > Also the inconsistencies between EXTLOG, GHES, BERT, and native error > reporting. >=20 Thanks for pointing these out. I will try to put all of these references in context for discussion. > > The third topic I would like to discuss is how we can get a set of comm= on > > benchmarks for memory tiering evaluations. Our team has done some initi= al > > work in this space, but we want to hear more from end users about their= =20 > > workloads of concern. There was a proposal related to this topic, but f= rom what=20 > > I understand no meeting has been held [3].=20 > >=20 > > The last topic that I believe is worth discussion is how do we come up = with > > a baseline for testing. I am aware of 3 efforts that could be used cxl_= test,=20 > > qemu, and uunit testing framework [4]. >=20 > I think benchmarking for memory-tiering is orthogonal to patch > unit, function, and integration testing. >=20 Agreed.=20 > For testing I think it is an "all of the above plus hardware testing if > possible" situation. My hope is to get to a point where CXL patchwork > lights up "S/W/F" columns with backend tests similar to NETDEV > patchwork: >=20 > https://patchwork.kernel.org/project/netdevbpf/list/ >=20 > There are some initial discussions about how to do this likely we can > grab some folks to discuss more. >=20 > I think Paul and Song would be useful to have for this discussion. Can > you recommend others that would be useful for this or other CXL > topics to help with timeslot conflict resolution? >=20 Luis already chimed in and he is definitely our expert in terms of establishing baselines for new functionalities.=20