From: Samuel Holland <samuel.holland@sifive.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, Alexandre Ghiti <alexghiti@rivosinc.com>
Subject: Re: [PATCH v4 12/12] riscv: mm: Always use an ASID to flush mm contexts
Date: Thu, 4 Jan 2024 09:50:48 -0600 [thread overview]
Message-ID: <e0ceb2e3-ae27-47aa-94de-f0d0060b2a77@sifive.com> (raw)
In-Reply-To: <ZZV3AAY3WIAq+sl9@xhacker>
On 2024-01-03 9:02 AM, Jisheng Zhang wrote:
> On Tue, Jan 02, 2024 at 02:00:49PM -0800, Samuel Holland wrote:
>> Even if multiple ASIDs are not supported, using the single-ASID variant
>> of the sfence.vma instruction preserves TLB entries for global (kernel)
>> pages. So it is always more efficient to use the single-ASID code path.
>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>> Changes in v4:
>> - There is now only one copy of __flush_tlb_range()
>>
>> Changes in v2:
>> - Update both copies of __flush_tlb_range()
>>
>> arch/riscv/include/asm/mmu_context.h | 2 --
>> arch/riscv/mm/context.c | 3 +--
>> arch/riscv/mm/tlbflush.c | 3 +--
>> 3 files changed, 2 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h
>> index 7030837adc1a..b0659413a080 100644
>> --- a/arch/riscv/include/asm/mmu_context.h
>> +++ b/arch/riscv/include/asm/mmu_context.h
>> @@ -33,8 +33,6 @@ static inline int init_new_context(struct task_struct *tsk,
>> return 0;
>> }
>>
>> -DECLARE_STATIC_KEY_FALSE(use_asid_allocator);
>> -
>> #include <asm-generic/mmu_context.h>
>>
>> #endif /* _ASM_RISCV_MMU_CONTEXT_H */
>> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
>> index 3ca9b653df7d..20057085ab8a 100644
>> --- a/arch/riscv/mm/context.c
>> +++ b/arch/riscv/mm/context.c
>> @@ -18,8 +18,7 @@
>>
>> #ifdef CONFIG_MMU
>>
>> -DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
>> -
>> +static DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
>
> One of my optimization "riscv: tlb: avoid tlb flushing if fullmm == 1"
> will make use of use_asid_allocator, so could we remove this modification?
Yes, I can leave the global declaration alone for now.
>> static unsigned long num_asids;
>>
>> static atomic_long_t current_version;
>> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
>> index 5ec621545c69..39d80f56d292 100644
>> --- a/arch/riscv/mm/tlbflush.c
>> +++ b/arch/riscv/mm/tlbflush.c
>> @@ -84,8 +84,7 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
>> if (cpumask_empty(cmask))
>> return;
>>
>> - if (static_branch_unlikely(&use_asid_allocator))
>> - asid = cntx2asid(atomic_long_read(&mm->context.id));
>> + asid = cntx2asid(atomic_long_read(&mm->context.id));
>> } else {
>> cmask = cpu_online_mask;
>> }
>> --
>> 2.42.0
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-01-04 15:50 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-02 22:00 [PATCH v4 00/12] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2024-01-02 22:00 ` [PATCH v4 01/12] riscv: Flush the instruction cache during SMP bringup Samuel Holland
2024-01-04 11:58 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 02/12] riscv: Use IPIs for remote cache/TLB flushes by default Samuel Holland
2024-01-04 12:09 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 03/12] riscv: mm: Broadcast kernel TLB flushes only when needed Samuel Holland
2024-01-04 12:15 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 04/12] riscv: Only send remote fences when some other CPU is online Samuel Holland
2024-01-03 14:57 ` Jisheng Zhang
2024-01-03 15:04 ` Jisheng Zhang
2024-01-04 12:33 ` Alexandre Ghiti
2024-01-04 15:33 ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 05/12] riscv: mm: Combine the SMP and UP TLB flush code Samuel Holland
2024-01-04 12:36 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2024-01-02 22:00 ` [PATCH v4 07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 Samuel Holland
2024-01-02 22:00 ` [PATCH v4 08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2024-01-04 12:39 ` Alexandre Ghiti
2024-01-04 15:42 ` Samuel Holland
2024-01-02 22:00 ` [PATCH v4 09/12] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2024-01-04 12:42 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 10/12] riscv: mm: Make asid_bits a local variable Samuel Holland
2024-01-03 15:00 ` Jisheng Zhang
2024-01-04 15:49 ` Samuel Holland
2024-01-04 12:47 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 11/12] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2024-01-04 12:55 ` Alexandre Ghiti
2024-01-02 22:00 ` [PATCH v4 12/12] riscv: mm: Always use an ASID to flush mm contexts Samuel Holland
2024-01-03 15:02 ` Jisheng Zhang
2024-01-04 15:50 ` Samuel Holland [this message]
2024-01-04 13:01 ` Alexandre Ghiti
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