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Fri, 24 Nov 2023 17:04:08 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.9.0-alpha0-1234-gac66594aae-fm-20231122.001-gac66594a MIME-Version: 1.0 Message-Id: In-Reply-To: <3iksuovvsln3cw3xpmjd7f7xixfvwaneu4ok56fnookvyolpco@wrxxew3thgnq> References: <20231122182419.30633-1-fancer.lancer@gmail.com> <20231122182419.30633-2-fancer.lancer@gmail.com> <8ca730b9-fa8c-46ea-bdc5-158da0f29c3a@app.fastmail.com> <245d3985-9085-4be0-8c74-d95d06334584@app.fastmail.com> <3iksuovvsln3cw3xpmjd7f7xixfvwaneu4ok56fnookvyolpco@wrxxew3thgnq> Date: Fri, 24 Nov 2023 22:03:49 +0000 From: "Jiaxun Yang" To: "Serge Semin" , "Thomas Bogendoerfer" Cc: "Arnd Bergmann" , "Andrew Morton" , "Mike Rapoport" , "Matthew Wilcox" , "Tiezhu Yang" , "Huacai Chen" , "Yinglu Yang" , "Alexey Malahov" , "Aleksandar Rikalo" , "Aleksandar Rikalo" , "Dragan Mladjenovic" , "Chao-ying Fu" , "Marc Zyngier" , "linux-mips@vger.kernel.org" , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/7] mips: dmi: Fix early remap on MIPS32 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: AF9F1C0012 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: 4r8ijh5nm8cupdajwct588mw45k5fzfg X-HE-Tag: 1700863452-725121 X-HE-Meta: U2FsdGVkX1+km6sB8Pe0akx6rE6PK+DxTQg5aINm+yObMGxQqU+cq3deS/OKSt5BFnKHXcX1LhWESOtaBkwXO6DCBCGRNDa8fPTDXDxkad5X3BARsXXw3QkGrOlqPJiCd+0qjVzdJZYcTYNDZSVgrYj8D52/f93J6BQ/Sx7SoPBewDjz2m3TtJl0MyLWk1ZwvwwCHXHi9DZmvN9mFHZNdvADyGlRBTF6/3OEd4JGmjtLNbwv647BJ0aW83pAI0qPBVSfH/RMtcE7DFjtd4hbqQkhlddhxxf5VZsge6W26QW4SOlLY8zrWlevC4kRIU5sLfFX2Gmlcm9DxOs1bq00MSJwqdH+C3uBEglnzVdf/qjDBhiHbdCmX0ad5/mx0YkMtKte8dBwijIp6Y57ywv5HAssgzpSlzCXGnwwC9Ur0X0uETMpohUo9xO1eqrZarnRTkczMI2ishCW6iGwvCETltEKs5YcEolfBLGTfMASAtrKSfU5fBF0NzJW5lqrbpn/KFGOk3yZp9eqTKYj0UmtaqLTwRu93E6XJ/0VUi0QBdCtzvXYh0XZhq2ztOUZtlktGM+extZITzcxvROMPVzc+f/0SOaiMG+fGnI4+ugcTB5CTA9TP2v+ln/5Zo/pDKzf5lw7NnoIAdbpTkZgHmeuupuHo0u8J4QU0ufpZkg1vIlVtGQM5uIoFcHZgBmbcUuZSbK850HC4cklMza53AisqGjDDrcOZSibD2HpyMam5lStOoH7NDx6MACa1XJhXvlNgKx6WaGZjO/sIt6NyaX3QFrsfNtEw8wvQ75VqeezeTPBE3i0OC1B2SXm8Zzy5ElG/JmHrknSAXM6mRUk9B5xwhNGFEq4J5JxLLvbUP6cL1Hub3jx2SNVeiC58xeBqiOhYU9jTCxtjkiU9sm3iCnZUMN2mrva96esln+dHGRbUNau8/DqCBCa01tq2a+aBe/DuPu6hpbvyuSWinEfNqk F5d6fHmW l6kLlLorW6DHioeDJ6HdWgRZ14lcMgpQa8rShWVTS61nit1EGm09i2YffUKpw+kxd7NAZMb4XbW+KooSOElz6opZgJF/f1NETZ8vEFTIWcc8DOP+2v9N6ouvIezMx1as0ZDTs1I8kAKsyhYvzl9CfZnT98Aed108dPUJsgy03fRMzschVvAhhLsKJZVXty2vvF+oSVKMK+OXzZYz8EyI4YTy5n6DuTd6ajSC1cHH3KFi2XfOXz9KZEMj5k2FUvO4hWhwCpD8gmiiA9MWi53p8CjXLgCjgdbVpYk0izDu/yVeyLg9o2jUwsskdRmxXKLQOpTMQMASYm+yQJ6lj2oEBIWKp4w== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: =E5=9C=A82023=E5=B9=B411=E6=9C=8824=E6=97=A5=E5=8D=81=E4=B8=80=E6=9C=88 = =E4=B8=8B=E5=8D=886:52=EF=BC=8CSerge Semin=E5=86=99=E9=81=93=EF=BC=9A > On Thu, Nov 23, 2023 at 05:33:31PM +0000, Jiaxun Yang wrote: >>=20 [...] >> Actually dmi_setup() is called before cpu_cache_init(). > > To preliminary sum the discussion, indeed there can be issues on the > platforms which have DMI initialized on the cached region. Here are > several solutions and additional difficulties I think may be caused by > implementing them: Thanks for such detailed conclusion! I'd prefer go solution 1, with comments below. > > 1. Use unmapped cached region utilization in the MIPS32 ioremap_prot() > method. > This solution a bit clumsy than it looks on the first glance. > ioremap_prot() can be used for various types of the cachability > mapping. Currently it's a default-cacheable CA preserved in the > _page_cachable_default variable and Write-combined CA saved in > boot_cpu_data.writecombine. Based on that we would have needed to use > the unmapped cached region utilized for the IO-remaps called with the > "_page_cachable_default" mapping flags passed only. The rest of the IO > range mappings, including the write-combined ones, would have been > handled by VM means. This would have made the ioremap_prot() a bit > less maintainable, but still won't be that hard to implement (unless I > miss something): > --- a/arch/mips/mm/ioremap.c > +++ b/arch/mips/mm/ioremap.c > /* > - * Map uncached objects in the low 512mb of address space usin= g KSEG1, > - * otherwise map using page tables. > + * Map uncached/default-cached objects in the low 512mb of add= ress > + * space using KSEG1/KSEG0, otherwise map using page tables. > */ > - if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) && > - flags =3D=3D _CACHE_UNCACHED) > - return (void __iomem *) CKSEG1ADDR(phys_addr); > + if (IS_LOW512(phys_addr) && IS_LOW512(last_addr)) { > + if (flags =3D=3D _CACHE_UNCACHED) > + return (void __iomem *) CKSEG1ADDR(phys_addr); > + else if (flags =3D=3D _page_cachable_default) > + return (void __iomem *) CKSEG0ADDR(phys_addr); > + } > > Currently I can't figure out what obvious problems it may cause. But > It seems suspicious that the cacheable IO-mapping hasn't been > implemented by the unmapped cacheable region in the first place. In > anyway this solution looks more dangerous than solution 2. because it > affects all the MIPS32 platforms at once. I just made a quick grep in tree, and it seems like we don't have much user of ioremap_cache (as well as ioremap_uc/wc) here so I think it is a safe assumption. > > 2. Convert dmi_remap_early() to ioremap_uc() (actually just ioremap() > as noted by Arnd). > As Jiaxun correctly noted this may cause problems on the platforms > which don't flush caches before jumping out to the kernel. Thomas said > that kernel flushes the caches early on boot, but Jiaxun noted that > it's still done after early DMI setup. So the issue with solution 2 is > that the setup_arch() method calls dmi_setup() before it flushes the > caches by means of the cpu_cache_init() method. I guess it can be > fixed just by moving the dmi_setup() method invocation to be after the > cpu_cache_init() is called. This solution looks much less invasive > than solution 1. I recall Tiezhu made dmi_setup() here for reasons. The first reason is t= hat DMI is placed at memory space that is not reserved, so it may get clobbe= red after mm is up. The second is we may have some early quirks depends on D= MI information. Thanks. > > So what do you think? What solution do you prefer? Perhaps > alternative? > > -Serge(y) > >>=20 >> Thanks >> > >> > Thomas. >> > >> > --=20 >> > Crap can work. Given enough thrust pigs will fly, but it's not nece= ssarily a >> > good idea. [ RFC1925= , 2.3 ] >>=20 >> --=20 >> - Jiaxun --=20 - Jiaxun