From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Peter Zijlstra <peterz@infradead.org>,
Michael Kelley <mhklinux@outlook.com>
Cc: "riel@surriel.com" <riel@surriel.com>,
"x86@kernel.org" <x86@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"zhengqi.arch@bytedance.com" <zhengqi.arch@bytedance.com>,
"nadav.amit@gmail.com" <nadav.amit@gmail.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"kernel-team@meta.com" <kernel-team@meta.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"jannh@google.com" <jannh@google.com>
Subject: Re: [PATCH v5 00/12] AMD broadcast TLB invalidation
Date: Fri, 17 Jan 2025 00:00:33 +0000 [thread overview]
Message-ID: <da35b3a2-6b48-4cf9-a6f8-39e28a3b022f@citrix.com> (raw)
In-Reply-To: <20250116223748.GA33629@noisy.programming.kicks-ass.net>
On 16/01/2025 10:37 pm, Peter Zijlstra wrote:
> On Thu, Jan 16, 2025 at 06:14:00PM +0000, Michael Kelley wrote:
>> So CoCo
>> VMs may still use the paravirtualization that makes hypercalls to do
>> TLB flushes. It's future work to *always* use INVLPGB (if available)
>> in a CoCo VM.
> That would place a limit on the number of CPUs, to be no larger than the
> number of available ASIDs.
Can you please be specific between PCID (the x86 architectural thing
commonly called ASID) or ASID (the thing named by the AMD architecture).
INVLPGB instruction under virt can use PCIDs to its hearts content, but
ASIDs are rewritten behind the scenes because VM does not usually know
the ASID the VMM assigned to it.
~Andrew
next prev parent reply other threads:[~2025-01-17 0:00 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 2:30 Rik van Riel
2025-01-16 2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16 2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16 2:30 ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-17 19:23 ` Michael Kelley
2025-01-17 19:32 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16 2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-16 2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16 2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16 2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16 2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20 9:56 ` Nadav Amit
2025-01-20 14:02 ` Rik van Riel
2025-01-20 14:14 ` Nadav Amit
2025-01-20 16:11 ` Rik van Riel
2025-01-20 17:09 ` Nadav Amit
2025-01-20 17:11 ` Rik van Riel
2025-01-20 17:50 ` Nadav Amit
2025-01-20 17:56 ` Rik van Riel
2025-01-20 18:56 ` Nadav Amit
2025-01-21 2:33 ` Rik van Riel
2025-01-16 2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16 2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37 ` Peter Zijlstra
2025-01-17 0:00 ` Andrew Cooper [this message]
2025-01-21 10:45 ` Peter Zijlstra
2025-01-21 17:14 ` Dave Hansen
2025-01-21 21:24 ` Michael Kelley
2025-01-21 17:22 ` Jann Horn
2025-01-21 21:39 ` Michael Kelley
2025-01-21 21:56 ` Jann Horn
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