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Violators will be prosecuted for from ; Mon, 10 Jul 2017 13:07:16 +1000 Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v6A37Dkx18087966 for ; Mon, 10 Jul 2017 13:07:13 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v6A373QS003769 for ; Mon, 10 Jul 2017 13:07:04 +1000 From: Anshuman Khandual Subject: Re: [RFC v5 38/38] Documentation: PowerPC specific updates to memory protection keys References: <1499289735-14220-1-git-send-email-linuxram@us.ibm.com> <1499289735-14220-39-git-send-email-linuxram@us.ibm.com> Date: Mon, 10 Jul 2017 08:37:04 +0530 MIME-Version: 1.0 In-Reply-To: <1499289735-14220-39-git-send-email-linuxram@us.ibm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-Id: Sender: owner-linux-mm@kvack.org List-ID: To: Ram Pai , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, x86@kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, khandual@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, bsingharora@gmail.com, dave.hansen@intel.com, hbabu@us.ibm.com, arnd@arndb.de, akpm@linux-foundation.org, corbet@lwn.net, mingo@redhat.com On 07/06/2017 02:52 AM, Ram Pai wrote: > Add documentation updates that capture PowerPC specific changes. > > Signed-off-by: Ram Pai > --- > Documentation/vm/protection-keys.txt | 85 ++++++++++++++++++++++++++-------- > 1 files changed, 65 insertions(+), 20 deletions(-) > > diff --git a/Documentation/vm/protection-keys.txt b/Documentation/vm/protection-keys.txt > index b643045..d50b6ab 100644 > --- a/Documentation/vm/protection-keys.txt > +++ b/Documentation/vm/protection-keys.txt > @@ -1,21 +1,46 @@ > -Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature > -which will be found on future Intel CPUs. > +Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature found in > +new generation of intel CPUs and on PowerPC 7 and higher CPUs. > > Memory Protection Keys provides a mechanism for enforcing page-based > -protections, but without requiring modification of the page tables > -when an application changes protection domains. It works by > -dedicating 4 previously ignored bits in each page table entry to a > -"protection key", giving 16 possible keys. > - > -There is also a new user-accessible register (PKRU) with two separate > -bits (Access Disable and Write Disable) for each key. Being a CPU > -register, PKRU is inherently thread-local, potentially giving each > -thread a different set of protections from every other thread. > - > -There are two new instructions (RDPKRU/WRPKRU) for reading and writing > -to the new register. The feature is only available in 64-bit mode, > -even though there is theoretically space in the PAE PTEs. These > -permissions are enforced on data access only and have no effect on > +protections, but without requiring modification of the page tables when an > +application changes protection domains. > + > + > +On Intel: > + > + It works by dedicating 4 previously ignored bits in each page table > + entry to a "protection key", giving 16 possible keys. > + > + There is also a new user-accessible register (PKRU) with two separate > + bits (Access Disable and Write Disable) for each key. Being a CPU > + register, PKRU is inherently thread-local, potentially giving each > + thread a different set of protections from every other thread. > + > + There are two new instructions (RDPKRU/WRPKRU) for reading and writing > + to the new register. The feature is only available in 64-bit mode, > + even though there is theoretically space in the PAE PTEs. These > + permissions are enforced on data access only and have no effect on > + instruction fetches. > + > + > +On PowerPC: > + > + It works by dedicating 5 page table entry bits to a "protection key", > + giving 32 possible keys. > + > + There is a user-accessible register (AMR) with two separate bits; > + Access Disable and Write Disable, for each key. Being a CPU > + register, AMR is inherently thread-local, potentially giving each > + thread a different set of protections from every other thread. NOTE: > + Disabling read permission does not disable write and vice-versa. We can only enable/disable entire access or write. Then how read permission can be changed with protection keys directly ? -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org