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From: Guenter Roeck <linux@roeck-us.net>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: linux-mm@kvack.org, akpm@linux-foundation.org,
	mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org,
	kaleshsingh@google.com, npiggin@gmail.com,
	joel@joelfernandes.org,
	Christophe Leroy <christophe.leroy@csgroup.eu>
Subject: Re: [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument
Date: Mon, 17 May 2021 06:38:34 -0700	[thread overview]
Message-ID: <d830fce9-c00a-e879-4115-94a2346a806f@roeck-us.net> (raw)
In-Reply-To: <e0eba73a-c2df-71c3-e03d-d4074d908fca@linux.ibm.com>

On 5/17/21 1:40 AM, Aneesh Kumar K.V wrote:
> On 5/15/21 10:05 PM, Guenter Roeck wrote:
>> On Thu, Apr 22, 2021 at 11:13:19AM +0530, Aneesh Kumar K.V wrote:
>>> No functional change in this patch
>>>
>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>>> ---
>>>   .../include/asm/book3s/64/tlbflush-radix.h    | 19 +++++++-----
>>>   arch/powerpc/include/asm/book3s/64/tlbflush.h | 23 ++++++++++++---
>>>   arch/powerpc/mm/book3s64/radix_hugetlbpage.c  |  4 +--
>>>   arch/powerpc/mm/book3s64/radix_tlb.c          | 29 +++++++------------
>>>   4 files changed, 42 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>>> index 8b33601cdb9d..171441a43b35 100644
>>> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>>> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>>> @@ -56,15 +56,18 @@ static inline void radix__flush_all_lpid_guest(unsigned int lpid)
>>>   }
>>>   #endif
>>> -extern void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma,
>>> -                       unsigned long start, unsigned long end);
>>> -extern void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
>>> -                     unsigned long end, int psize);
>>> -extern void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
>>> -                       unsigned long start, unsigned long end);
>>> -extern void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
>>> +void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma,
>>> +                    unsigned long start, unsigned long end,
>>> +                    bool flush_pwc);
>>> +void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
>>> +                unsigned long start, unsigned long end,
>>> +                bool flush_pwc);
>>> +void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start,
>>> +                      unsigned long end, int psize, bool flush_pwc);
>>> +void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
>>>                   unsigned long end);
>>> -extern void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end);
>>> +void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end);
>>> +
>>>   extern void radix__local_flush_tlb_mm(struct mm_struct *mm);
>>>   extern void radix__local_flush_all_mm(struct mm_struct *mm);
>>> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h b/arch/powerpc/include/asm/book3s/64/tlbflush.h
>>> index 215973b4cb26..f9f8a3a264f7 100644
>>> --- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
>>> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
>>> @@ -45,13 +45,30 @@ static inline void tlbiel_all_lpid(bool radix)
>>>           hash__tlbiel_all(TLB_INVAL_SCOPE_LPID);
>>>   }
>>> +static inline void flush_pmd_tlb_pwc_range(struct vm_area_struct *vma,
>>                   ^^^^
>>> +                       unsigned long start,
>>> +                       unsigned long end,
>>> +                       bool flush_pwc)
>>> +{
>>> +    if (radix_enabled())
>>> +        return radix__flush_pmd_tlb_range(vma, start, end, flush_pwc);
>>> +    return hash__flush_tlb_range(vma, start, end);
>>          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>
>>> +}
> 
> In this specific case we won't have  build errors because,
> 
> static inline void hash__flush_tlb_range(struct vm_area_struct *vma,
>                       unsigned long start, unsigned long end)
> {
> 

Sorry, you completely lost me.

Building parisc:allnoconfig ... failed
--------------
Error log:
In file included from arch/parisc/include/asm/cacheflush.h:7,
                  from include/linux/highmem.h:12,
                  from include/linux/pagemap.h:11,
                  from include/linux/ksm.h:13,
                  from mm/mremap.c:14:
mm/mremap.c: In function 'flush_pte_tlb_pwc_range':
arch/parisc/include/asm/tlbflush.h:20:2: error: 'return' with a value, in function returning void

Guenter

> 
> But I agree the below is better to read.
> 
> static inline void flush_pmd_tlb_pwc_range(struct vm_area_struct *vma,
>                         unsigned long start,
>                         unsigned long end,
>                         bool flush_pwc)
> {
>      if (radix_enabled())
>          radix__flush_pmd_tlb_range(vma, start, end, flush_pwc);
>      else
>          hash__flush_tlb_range(vma, start, end);
>      return
> }
> 
>>
>>>   #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
>>>   static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
>>                   ^^^^
>>>                          unsigned long start, unsigned long end)
>>> +{
>>> +    return flush_pmd_tlb_pwc_range(vma, start, end, false);
>>          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>
>> Doesn't that cause build warnings/errors all over the place ?
>>
>> Guenter
>>
> 
> 
> -aneesh



  reply	other threads:[~2021-05-17 13:38 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-22  5:43 [PATCH v5 0/9] Speedup mremap on ppc64 Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 1/9] selftest/mremap_test: Update the test to handle pagesize other than 4K Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 2/9] selftest/mremap_test: Avoid crash with static build Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 3/9] mm/mremap: Use pmd/pud_poplulate to update page table entries Aneesh Kumar K.V
2021-05-18 20:04   ` Nathan Chancellor
2021-05-19  4:46     ` Aneesh Kumar K.V
2021-05-19 18:02       ` Nathan Chancellor
2021-05-20  2:18       ` Peter Xu
2021-05-20  8:26         ` Aneesh Kumar K.V
2021-05-20 12:46           ` Peter Xu
2021-05-20 13:23             ` Aneesh Kumar K.V
2021-05-20 13:37               ` Aneesh Kumar K.V
2021-05-20 14:57                 ` Peter Xu
2021-05-20 19:06                   ` Zi Yan
2021-05-20 20:01                     ` Peter Xu
2021-05-20 20:25                       ` Kalesh Singh
2021-04-22  5:43 ` [PATCH v5 4/9] powerpc/mm/book3s64: Fix possible build error Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument Aneesh Kumar K.V
2021-05-15 16:35   ` Guenter Roeck
2021-05-15 20:41     ` Andrew Morton
2021-05-15 23:05       ` Guenter Roeck
2021-05-17  8:40     ` Aneesh Kumar K.V
2021-05-17 13:38       ` Guenter Roeck [this message]
2021-05-17 13:55         ` Aneesh Kumar K.V
2021-05-17 14:18           ` Guenter Roeck
2021-05-19  0:26             ` Michael Ellerman
2021-05-19  0:45               ` Segher Boessenkool
2021-05-19 12:03                 ` Segher Boessenkool
2021-05-19 13:37                   ` Guenter Roeck
2021-05-19 14:20                     ` Segher Boessenkool
2021-05-19 15:28                       ` Guenter Roeck
2021-05-20  7:37                   ` Michael Ellerman
2021-05-20 12:17                     ` Segher Boessenkool
2021-05-19  1:08               ` Guenter Roeck
2021-05-20 11:38                 ` Michael Ellerman
2021-05-20 11:56                   ` Guenter Roeck
2021-04-22  5:43 ` [PATCH v5 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Aneesh Kumar K.V
2021-05-20 15:26   ` Aneesh Kumar K.V
2021-05-20 16:57     ` Aneesh Kumar K.V
2021-05-21  2:40       ` Linus Torvalds
2021-05-21  3:03         ` Aneesh Kumar K.V
2021-05-21  3:28           ` Aneesh Kumar K.V
2021-05-21  6:13           ` Linus Torvalds
2021-05-21 12:50             ` Aneesh Kumar K.V
2021-05-21 13:03               ` Aneesh Kumar K.V
2021-05-21 16:03                 ` Linus Torvalds
2021-05-21 16:29                   ` Aneesh Kumar K.V
2021-05-24 14:24                   ` Aneesh Kumar K.V
2021-05-21 15:24               ` Liam Howlett
2021-05-21 16:02                 ` Aneesh Kumar K.V
2021-05-21 16:05                 ` Linus Torvalds
2021-04-22  5:43 ` [PATCH v5 8/9] mm/mremap: Allow arch runtime override Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 9/9] powerpc/mm: Enable move pmd/pud Aneesh Kumar K.V
2021-05-11 22:19   ` Andrew Morton

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