Re: [LSF/MM] CXL Boot to Bash - Section 0: ACPI and Linux Resources

[Dave Jiang <dave.jiang@intel.com>]

On 3/5/25 4:34 PM, Gregory Price wrote:
> On Wed, Mar 05, 2025 at 03:44:13PM -0700, Dave Jiang wrote:
>>
>>
>> On 3/5/25 3:20 PM, Gregory Price wrote:
>>> --------------------
>>> Part 0: ACPI Tables.
>>> --------------------
>>> I considered publishing this section first, or at least under
>>> "Platform", but I've found this information largely useful in
>>> debugging interleave configurations and tiering mechanisms -
>>> which are higher level concepts.
>>
>> Hi Gregory,
>> Thanks for detailing all this information. It has been a really good read.
>>
>> Do you intend to also add CDAT information and device performance data calculation related to that? The SRAT/HMAT info only covers CXL memory that are already setup by the BIOS as system memory. Otherwise it only contains performance data for the Generic Port and not the rest of the path to the endpoint.
>>
> 
> Probably CDAT should land in here as well, though in the context of
> simple volatile memory devices it seemed a bit overkill to include it.
> 
> I also don't have a ton of exposure to the GenPort flow of operations,
> so i didn't want to delay what I do have here.  If you have a
> recommended addition - I do intend to go through and edit/reformat most
> of this series after LSF/MM into a friendlier format of documentation.

I can help write it if there's no great urgency. I'll try to find some time creating a draft and send it your way.

DJ

> 
> I wanted to avoid dropping a 50 page writeup all at once with hopes of
> getting feedback on each chunk to correct inaccuracies (see hotplug). So
> I'm certainly open to adding whatever folks think is missing/important.
> 
> ~Gregory