Re: [PATCH 0/4] memcg: nmi-safe kmem charging

[Shakeel Butt <shakeel.butt@linux.dev>]

On Tue, May 13, 2025 at 01:41:25PM +0200, Peter Zijlstra wrote:
> On Tue, May 13, 2025 at 09:15:23AM +0200, Vlastimil Babka wrote:
> 
> > >> > The initial prototype tried to make memcg charging infra for kernel
> > >> > memory re-entrant against irq and nmi. However upon realizing that
> > >> > this_cpu_* operations are not safe on all architectures (Tejun), this
> > >> 
> > >> I assume it was an off-list discussion?
> > >> Could we avoid this for the architectures where these are safe, which should
> > >> be the major ones I hope?
> 
> IIRC Power64 has issues here, 'funnily' their local_t is NMI safe.
> Perhaps we could do the same for their this_cpu_*(), but ideally someone
> with actual power hardware should do this ;-)
> 

Is CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS the right config to
differentiate between such archs? I see Power64 does not have that
enabled.

> > > Yes it was an off-list discussion. The discussion was more about the
> > > this_cpu_* ops vs atomic_* ops as on x86 this_cpu_* does not have lock
> > > prefix and how I should prefer this_cpu_* over atomic_* for my series on
> > > objcg charging without disabling irqs. Tejun pointed out this_cpu_* are
> > > not nmi safe for some archs and it would be better to handle nmi context
> > > separately. So, I am not that worried about optimizing for NMI context
> > 
> > Well, we're introducing in_nmi() check and different execution paths to all
> > charging. This could be e.g. compiled out for architectures where this_cpu*
> > is NMI safe or they don't have NMIs in the first place.
> 
> Very few architectures one would care about do not have NMIs. Risc-V
> seems to be the exception here ?!?
> 
> > > but your next comment on generic_atomic64_* ops is giving me headache.
> > > 
> > >> 
> > >> > series took a different approach targeting only nmi context. Since the
> > >> > number of stats that are updated in kernel memory charging path are 3,
> > >> > this series added special handling of those stats in nmi context rather
> > >> > than making all >100 memcg stats nmi safe.
> > >> 
> > >> Hmm so from patches 2 and 3 I see this relies on atomic64_add().
> > >> But AFAIU lib/atomic64.c has the generic fallback implementation for
> > >> architectures that don't know better, and that would be using the "void
> > >> generic_atomic64_##op" macro, which AFAICS is doing:
> > >> 
> > >>         local_irq_save(flags);                                          \
> > >>         arch_spin_lock(lock);                                           \
> > >>         v->counter c_op a;                                              \
> > >>         arch_spin_unlock(lock);                                         \
> > >>         local_irq_restore(flags);                                       \
> > >> 
> > >> so in case of a nmi hitting after the spin_lock this can still deadlock?
> > >> 
> > >> Hm or is there some assumption that we only use these paths when already
> > >> in_nmi() and then another nmi can't come in that context?
> > >> 
> > >> But even then, flush_nmi_stats() in patch 1 isn't done in_nmi() and uses
> > >> atomic64_xchg() which in generic_atomic64_xchg() implementation also has the
> > >> irq_save+spin_lock. So can't we deadlock there?
> > > 
> > > I was actually assuming that atomic_* ops are safe against nmis for all
> > > archs.
> 
> We have HAVE_NMI_SAFE_CMPXCHG for this -- there are architectures where
> this is not the case -- but again, those are typically oddball archs you
> don't much care about.
> 
> But yes, *64 on 32bit archs is generally not NMI safe.
> 
> > I looked at atomic_* ops in include/asm-generic/atomic.h and it
> > > is using arch_cmpxchg() for CONFIG_SMP and it seems like for archs with
> > > cmpxchg should be fine against nmi. I am not sure why atomic64_* are not
> > > using arch_cmpxchg() instead. I will dig more.
> 
> Not many 32bit architectures have 64bit cmpxchg. We're only now dropping
> support for x86 chips without CMPXCHG8b.
> 

As Vlastimil pointed out (last point), I don't think I will need 64bit
cmpxchg, 32bit cmpxchg will be fine.

> > Yeah I've found https://docs.kernel.org/core-api/local_ops.html and since it
> > listed Mathieu we discussed on IRC and he mentioned the same thing that
> > atomic_ ops are fine, but the later added 64bit variant isn't, which PeterZ
> > (who added it) acknowledged.
> > 
> > But there could be way out if we could somehow compile-time assert that
> > either is true:
> > - CONFIG_HAVE_NMI=n - we can compile out all the nmi code
> 
> Note that in_nmi() is not depending on HAVE_NMI -- nor can it be. Many
> architectures treat various traps as NMI-like, even though they might
> not have real NMIs.
> 
> > - this_cpu is safe on that arch - we can also compile out the nmi code
> 
> There is no config symbol for this presently.

Hmm what about CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS?

> 
> > - (if the above leaves any 64bit arch) its 64bit atomics implementation is safe
> 
> True, only because HPPA does not in fact have NMIs.

What is HPPA?

> 
> > - (if there are any 32bit applicable arch left) 32bit atomics should be
> > enough for the nmi counters even with >4GB memory as we flush them? and we
> > know the 32bit ops are safe
> 
> Older ARM might qualify here.

Thanks a lot Vlastimil & Peter for the suggestions. Let me summarize
what I plan to do and please point out if I am doing something wrong:


#if defined(CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS) || !defined(CONFIG_HAVE_NMI)

// Do normal this_cpu* ops

#elif defined(ARCH_HAVE_NMI_SAFE_CMPXCHG)

// Do 32 bit atomic ops with in_nmi() checks

#else

// Build error or ignore nmi stats??

#endif


WDYT?

(BTW Vlastimil, I might rebase send out the irq-safe series before this
nmi one.)

thanks,
Shakeel