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From: Rik van Riel <riel@surriel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de,
	 dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com,
	nadav.amit@gmail.com, 	thomas.lendacky@amd.com,
	kernel-team@meta.com, linux-mm@kvack.org,
		akpm@linux-foundation.org, jannh@google.com,
	mhklinux@outlook.com, 	andrew.cooper3@citrix.com
Subject: Re: [PATCH v6 05/12] x86/mm: add INVLPGB support code
Date: Wed, 22 Jan 2025 11:58:26 -0500	[thread overview]
Message-ID: <cc6101619afe5f148b1575fb42807cb1b4766b6e.camel@surriel.com> (raw)
In-Reply-To: <20250121094540.GA5388@noisy.programming.kicks-ass.net>

On Tue, 2025-01-21 at 10:45 +0100, Peter Zijlstra wrote:
> On Sun, Jan 19, 2025 at 09:40:13PM -0500, Rik van Riel wrote:
> 
> > 
> > +static inline void __invlpgb(unsigned long asid, unsigned long
> > pcid,
> > +			     unsigned long addr, u16 extra_count,
> > +			     bool pmd_stride, unsigned long flags)
> > +{
> > +	u32 edx = (pcid << 16) | asid;
> > +	u32 ecx = (pmd_stride << 31) | extra_count;
> > +	u64 rax = addr | flags;
> > +
> > +	/* INVLPGB; supported in binutils >= 2.36. */
> > +	asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c"
> > (ecx), "d" (edx));
> > +}
> 
> So asid is always 0 (for now), but I'd feel better if that was a u16
> argument, less chance funnies when someone starts using it.
> 
> We should probably mask or WARN on addr having low bits set, and
> flags
> should then be a u8 or something.

Done and done. Thank you for the suggestions.

-- 
All Rights Reversed.


  reply	other threads:[~2025-01-22 16:59 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-20  2:40 [PATCH v6 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-01-20  2:40 ` [PATCH v6 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-20 19:32   ` David Hildenbrand
2025-01-20  2:40 ` [PATCH v6 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-20 19:47   ` David Hildenbrand
2025-01-21  1:03     ` Rik van Riel
2025-01-21  7:46       ` David Hildenbrand
2025-01-21  8:54         ` Peter Zijlstra
2025-01-22 15:48           ` Rik van Riel
2025-01-20  2:40 ` [PATCH v6 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-01-20  2:40 ` [PATCH v6 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-20  2:40 ` [PATCH v6 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-21  9:45   ` Peter Zijlstra
2025-01-22 16:58     ` Rik van Riel [this message]
2025-01-20  2:40 ` [PATCH v6 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-20  2:40 ` [PATCH v6 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-20  2:40 ` [PATCH v6 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-20  2:40 ` [PATCH v6 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-20 14:02   ` Nadav Amit
2025-01-20 16:09     ` Rik van Riel
2025-01-20 20:04       ` Nadav Amit
2025-01-20 22:44         ` Rik van Riel
2025-01-21  7:31           ` Nadav Amit
2025-01-21  9:55   ` Peter Zijlstra
2025-01-21 10:33     ` Peter Zijlstra
2025-01-23  1:40       ` Rik van Riel
2025-01-21 18:48     ` Dave Hansen
2025-01-22  8:38   ` Peter Zijlstra
2025-01-23  1:13     ` Rik van Riel
2025-01-23  9:07       ` Peter Zijlstra
2025-01-23 12:42         ` Rik van Riel
2025-01-20  2:40 ` [PATCH v6 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20  2:40 ` [PATCH v6 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-20  2:40 ` [PATCH v6 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-20  5:58 ` [PATCH v6 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-24 11:41 ` Manali Shukla

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