From: Rik van Riel <riel@surriel.com>
To: Tom Lendacky <thomas.lendacky@amd.com>, Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
peterz@infradead.org, dave.hansen@linux.intel.com,
zhengqi.arch@bytedance.com, nadav.amit@gmail.com,
kernel-team@meta.com, linux-mm@kvack.org,
akpm@linux-foundation.org, jackmanb@google.com,
jannh@google.com, mhklinux@outlook.com,
andrew.cooper3@citrix.com, Manali.Shukla@amd.com,
mingo@kernel.org
Subject: Re: [PATCH v13 06/14] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing
Date: Thu, 27 Feb 2025 20:13:49 -0500 [thread overview]
Message-ID: <c6a38a1b6f27ae787dbfd99df225f464c274590e.camel@surriel.com> (raw)
In-Reply-To: <2731f073-d529-7870-6d25-ebd2e44cd10c@amd.com>
On Wed, 2025-02-26 at 12:12 -0600, Tom Lendacky wrote:
>
> As long as you keep the ASID value in EDX[15:0] as 0, then you won't
> #GP. ASID 0 is the host/hypervisor. An ASID > 0 belongs to a guest.
>
I've been spending some time reading the KVM code,
and I don't think invlpgb would be currently useful
with KVM.
From reading pre_svm_run(), new_asid(), and svm_vcpu_run(),
it looks like the ASID number used might be different for
each VCPU, assigned on a per (physical host) CPU basis.
It would take some surgery to change that around.
Some googling around also suggests that the ASID address
space is even more limited than the PCID address space :(
--
All Rights Reversed.
next prev parent reply other threads:[~2025-02-28 1:15 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-23 19:48 [PATCH v13 00/14] AMD broadcast TLB invalidation Rik van Riel
2025-02-23 19:48 ` [PATCH v13 01/14] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-02-24 11:48 ` Borislav Petkov
2025-02-23 19:48 ` [PATCH v13 02/14] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-24 12:00 ` Borislav Petkov
2025-02-23 19:48 ` [PATCH v13 03/14] x86/mm: add INVLPGB support code Rik van Riel
2025-02-24 12:14 ` Borislav Petkov
2025-02-23 19:48 ` [PATCH v13 04/14] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-24 12:31 ` Borislav Petkov
2025-02-24 12:44 ` Nadav Amit
2025-02-23 19:48 ` [PATCH v13 05/14] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-24 12:46 ` Borislav Petkov
2025-02-23 19:48 ` [PATCH v13 06/14] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-24 13:27 ` Borislav Petkov
2025-02-25 19:17 ` Rik van Riel
2025-02-25 20:38 ` Borislav Petkov
2025-02-25 21:03 ` Borislav Petkov
2025-02-25 22:03 ` Rik van Riel
2025-02-26 17:00 ` Tom Lendacky
2025-02-26 17:02 ` Rik van Riel
2025-02-26 17:36 ` Tom Lendacky
2025-02-26 17:46 ` Rik van Riel
2025-02-26 18:12 ` Tom Lendacky
2025-02-26 22:01 ` Rik van Riel
2025-02-28 1:13 ` Rik van Riel [this message]
2025-02-28 15:02 ` Tom Lendacky
2025-02-28 15:57 ` Sean Christopherson
2025-02-28 20:42 ` Tom Lendacky
2025-02-23 19:48 ` [PATCH v13 07/14] x86/mm: global ASID allocation helper functions Rik van Riel
2025-02-24 14:16 ` Borislav Petkov
2025-02-25 20:22 ` Rik van Riel
2025-02-23 19:48 ` [PATCH v13 08/14] x86/mm: global ASID context switch & TLB flush handling Rik van Riel
2025-02-23 23:08 ` kernel test robot
2025-02-24 1:26 ` Rik van Riel
2025-02-24 2:01 ` Rik van Riel
2025-02-24 18:41 ` kernel test robot
2025-02-23 19:48 ` [PATCH v13 09/14] x86/mm: global ASID process exit helpers Rik van Riel
2025-02-23 19:49 ` [PATCH v13 10/14] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-02-23 19:49 ` [PATCH v13 11/14] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-02-23 19:49 ` [PATCH v13 12/14] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-02-23 19:49 ` [PATCH v13 13/14] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-02-23 19:49 ` [PATCH v13 14/14] x86/mm: add noinvlpgb commandline option Rik van Riel
2025-02-23 21:29 ` Borislav Petkov
2025-02-24 0:34 ` Rik van Riel
2025-02-24 6:29 ` Borislav Petkov
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