From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl0-f71.google.com (mail-pl0-f71.google.com [209.85.160.71]) by kanga.kvack.org (Postfix) with ESMTP id 777936B0005 for ; Tue, 22 May 2018 13:03:58 -0400 (EDT) Received: by mail-pl0-f71.google.com with SMTP id q16-v6so12507365pls.15 for ; Tue, 22 May 2018 10:03:58 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com. [134.134.136.100]) by mx.google.com with ESMTPS id b38-v6si16788760plb.541.2018.05.22.10.03.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 May 2018 10:03:57 -0700 (PDT) Subject: Re: [PATCH] mm: Add new vma flag VM_LOCAL_CPU References: <0efb5547-9250-6b6c-fe8e-cf4f44aaa5eb@netapp.com> <20180514191551.GA27939@bombadil.infradead.org> <7ec6fa37-8529-183d-d467-df3642bcbfd2@netapp.com> <20180515004137.GA5168@bombadil.infradead.org> <010001637399f796-3ffe3ed2-2fb1-4d43-84f0-6a65b6320d66-000000@email.amazonses.com> <5aea6aa0-88cc-be7a-7012-7845499ced2c@netapp.com> <50cbc27f-0014-0185-048d-25640f744b5b@linux.intel.com> <0100016388be5738-df8f9d12-7011-4e4e-ba5b-33973e5da794-000000@email.amazonses.com> From: Dave Hansen Message-ID: Date: Tue, 22 May 2018 10:03:54 -0700 MIME-Version: 1.0 In-Reply-To: <0100016388be5738-df8f9d12-7011-4e4e-ba5b-33973e5da794-000000@email.amazonses.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: owner-linux-mm@kvack.org List-ID: To: Christopher Lameter Cc: Boaz Harrosh , Jeff Moyer , Matthew Wilcox , Andrew Morton , "Kirill A. Shutemov" , linux-kernel , linux-fsdevel , "linux-mm@kvack.org" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Peter Zijlstra , Rik van Riel , Jan Kara , Matthew Wilcox , Amit Golander On 05/22/2018 09:46 AM, Christopher Lameter wrote: > On Tue, 22 May 2018, Dave Hansen wrote: > >> On 05/22/2018 09:05 AM, Boaz Harrosh wrote: >>> How can we implement "Private memory"? >> Per-cpu page tables would do it. > We already have that for percpu subsystem. See alloc_percpu() I actually mean a set of page tables which is only ever installed on a single CPU. The CPU is architecturally allowed to go load any PTE in the page tables into the TLB any time it feels like. The only way to keep a PTE from getting into the TLB is not ensure that a CPU never has any access to it, and the only way to do that is to make sure that no set of page tables it ever loads into CR3 have that PTE. As Peter said, it's possible, but not pretty.