Re: [PATCHv8 00/11] Linear Address Masking enabling

[Dave Hansen <dave.hansen@intel.com>]

On 9/23/22 08:28, Ashok Raj wrote:
>>
>> I thought devices also cached address translation responses from the
>> IOMMU and stashed them in their own device-local TLB.  If the device is
>> unaware of the tags, then how does device TLB invalidation work?  Would
> This is coming a full circle now :-)
> 
> Since the device doesn't understand tagging, SVM and tagging aren't
> compatible. If you need SVM, you can only send sanitized pointers to the
> device period. In fact our page-request even looks for canonical checks
> before doing the page-faulting.
> 
>> all device TLB flushes be full flushes of the devices TLB?  If something
>> tried to use single-address invalidation, it would need to invalidate
>> every possible tag alias because the device wouldn't know that the tags
>> *are* tags instead of actual virtual addresses.
> Once tagging is extended into the PCI SIG, and devices know to work with
> them, so will the IOMMU, then they can all play in the same field. Until
> then they are isolated, or let SVM only work with untagged VA's.

But, the point that Kirill and I were getting at is still that devices
*have* a role to play here.  The idea that this can be hidden at the
IOMMU layer is pure fantasy.  Right?