From: Dave Hansen <dave.hansen@intel.com>
To: Shivank Garg <shivankg@amd.com>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>
Cc: ardb@kernel.org, bp@alien8.de, brijesh.singh@amd.com,
corbet@lwn.net, dave.hansen@linux.intel.com, hpa@zytor.com,
jan.kiszka@siemens.com, jgross@suse.com, kbingham@kernel.org,
linux-doc@vger.kernel.org, linux-efi@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mm@kvack.org,
luto@kernel.org, michael.roth@amd.com, mingo@redhat.com,
peterz@infradead.org, rick.p.edgecombe@intel.com,
sandipan.das@amd.com, thomas.lendacky@amd.com, x86@kernel.org
Subject: Re: [PATCH 0/3] x86: Make 5-level paging support unconditional for x86-64
Date: Thu, 31 Oct 2024 08:36:00 -0700 [thread overview]
Message-ID: <c049fdad-14e0-4d03-aa33-9d975374268e@intel.com> (raw)
In-Reply-To: <5b031938-9c82-4f09-b5dc-c45bc7fe6e07@amd.com>
On 7/31/24 10:45, Shivank Garg wrote:
> It would also be nice to get perf traces. Maybe it is purely SW issue.
Cycle counts aren't going to help much here. For instance, if 5-level
paging makes *ALL* TLB misses slower, you would just see a regression in
any code that misses the TLB, which could show up all over.
On Intel we have some PMU events like this:
dtlb_store_misses.walk_active
[Cycles when at least one PMH is busy
with a page walk for a store]
(there's a load side one as well). If a page walk gets more expensive,
you can see it there. Note that this doesn't actually tell you how much
time the core spent _waiting_ for a page walk to complete. If all the
speculation magic works perfectly in your favor, you could have the PMH
busy 100% of cycles but never had the core waiting on it.
So could we drill down a level in the "perf traces" please, and gather
some of the relevant performance counters and not just cycles?
prev parent reply other threads:[~2024-10-31 15:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-31 8:57 Shivank Garg
2024-07-31 9:15 ` Thomas Gleixner
2024-07-31 11:11 ` Peter Zijlstra
2024-07-31 11:36 ` Kirill A. Shutemov
2024-07-31 11:40 ` Peter Zijlstra
2024-07-31 17:45 ` Shivank Garg
2024-10-31 15:36 ` Dave Hansen [this message]
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