[linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64

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* [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd)
@ 2023-07-27  5:10 Julia Lawall
  2023-07-27  8:34 ` Biju Das
  0 siblings, 1 reply; 6+ messages in thread
From: Julia Lawall @ 2023-07-27  5:10 UTC (permalink / raw)
  To: Biju Das; +Cc: Linux Memory Management List, Stephen Boyd, oe-kbuild-all



---------- Forwarded message ----------
Date: Thu, 27 Jul 2023 08:50:37 +0800
From: kernel test robot <lkp@intel.com>
To: oe-kbuild@lists.linux.dev
Cc: lkp@intel.com, Julia Lawall <julia.lawall@inria.fr>
Subject: [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8:
    WARNING: do_div() does a 64-by-32 division,
    please consider using div64_ul instead.

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: Linux Memory Management List <linux-mm@kvack.org>
TO: Biju Das <biju.das.jz@bp.renesas.com>
CC: Stephen Boyd <sboyd@kernel.org>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   0ba5d07205771c50789fd9063950aa75e7f1183f
commit: 6e9aff555db7b6816076121ac3feebc3006de9ad [2742/4710] clk: Add support for versa3 clock driver
:::::: branch date: 19 hours ago
:::::: commit date: 7 days ago
config: sparc64-randconfig-r061-20230726 (https://download.01.org/0day-ci/archive/20230727/202307270841.yr5HxYIl-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230727/202307270841.yr5HxYIl-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Julia Lawall <julia.lawall@inria.fr>
| Closes: https://lore.kernel.org/r/202307270841.yr5HxYIl-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.

vim +404 drivers/clk/clk-versaclock3.c

6e9aff555db7b6 Biju Das 2023-07-05  382
6e9aff555db7b6 Biju Das 2023-07-05  383  static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
6e9aff555db7b6 Biju Das 2023-07-05  384  			       unsigned long *parent_rate)
6e9aff555db7b6 Biju Das 2023-07-05  385  {
6e9aff555db7b6 Biju Das 2023-07-05  386  	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
6e9aff555db7b6 Biju Das 2023-07-05  387  	const struct vc3_pll_data *pll = vc3->data;
6e9aff555db7b6 Biju Das 2023-07-05  388  	u64 div_frc;
6e9aff555db7b6 Biju Das 2023-07-05  389
6e9aff555db7b6 Biju Das 2023-07-05  390  	if (rate < pll->vco_min)
6e9aff555db7b6 Biju Das 2023-07-05  391  		rate = pll->vco_min;
6e9aff555db7b6 Biju Das 2023-07-05  392  	if (rate > pll->vco_max)
6e9aff555db7b6 Biju Das 2023-07-05  393  		rate = pll->vco_max;
6e9aff555db7b6 Biju Das 2023-07-05  394
6e9aff555db7b6 Biju Das 2023-07-05  395  	vc3->div_int = rate / *parent_rate;
6e9aff555db7b6 Biju Das 2023-07-05  396
6e9aff555db7b6 Biju Das 2023-07-05  397  	if (pll->num == VC3_PLL2) {
6e9aff555db7b6 Biju Das 2023-07-05  398  		if (vc3->div_int > 0x7ff)
6e9aff555db7b6 Biju Das 2023-07-05  399  			rate = *parent_rate * 0x7ff;
6e9aff555db7b6 Biju Das 2023-07-05  400
6e9aff555db7b6 Biju Das 2023-07-05  401  		/* Determine best fractional part, which is 16 bit wide */
6e9aff555db7b6 Biju Das 2023-07-05  402  		div_frc = rate % *parent_rate;
6e9aff555db7b6 Biju Das 2023-07-05  403  		div_frc *= BIT(16) - 1;
6e9aff555db7b6 Biju Das 2023-07-05 @404  		do_div(div_frc, *parent_rate);
6e9aff555db7b6 Biju Das 2023-07-05  405
6e9aff555db7b6 Biju Das 2023-07-05  406  		vc3->div_frc = (u32)div_frc;
6e9aff555db7b6 Biju Das 2023-07-05  407  		rate = (*parent_rate *
6e9aff555db7b6 Biju Das 2023-07-05  408  			(vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
6e9aff555db7b6 Biju Das 2023-07-05  409  	} else {
6e9aff555db7b6 Biju Das 2023-07-05  410  		rate = *parent_rate * vc3->div_int;
6e9aff555db7b6 Biju Das 2023-07-05  411  	}
6e9aff555db7b6 Biju Das 2023-07-05  412
6e9aff555db7b6 Biju Das 2023-07-05  413  	return rate;
6e9aff555db7b6 Biju Das 2023-07-05  414  }
6e9aff555db7b6 Biju Das 2023-07-05  415

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd)
  2023-07-27  5:10 [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd) Julia Lawall
@ 2023-07-27  8:34 ` Biju Das
  2023-07-27  8:43   ` Julia Lawall
  0 siblings, 1 reply; 6+ messages in thread
From: Biju Das @ 2023-07-27  8:34 UTC (permalink / raw)
  To: Julia Lawall; +Cc: Linux Memory Management List, Stephen Boyd, oe-kbuild-all

Hi,

The reproduce link is not working for me.

https://download.01.org/0day-ci/archive/20230727/202307270841.yr5HxYIl-lkp@intel.com/reproduce

Can you please provide instruction to reproduce this issue?

Cheers,
Biju

> versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division,
> please consider using div64_ul instead. (fwd)
> 
> 
> 
> ---------- Forwarded message ----------
> Date: Thu, 27 Jul 2023 08:50:37 +0800
> From: kernel test robot <lkp@intel.com>
> To: oe-kbuild@lists.linux.dev
> Cc: lkp@intel.com, Julia Lawall <julia.lawall@inria.fr>
> Subject: [linux-next:master 2742/4710] drivers/clk/clk-
> versaclock3.c:404:2-8:
>     WARNING: do_div() does a 64-by-32 division,
>     please consider using div64_ul instead.
> 
> BCC: lkp@intel.com
> CC: oe-kbuild-all@lists.linux.dev
> CC: Linux Memory Management List <linux-mm@kvack.org>
> TO: Biju Das <biju.das.jz@bp.renesas.com>
> CC: Stephen Boyd <sboyd@kernel.org>
> 
> tree:
> 
> If you fix the issue in a separate patch/commit (i.e. not just a new
> version of the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Reported-by: Julia Lawall <julia.lawall@inria.fr>
> | Closes:
%2BsY49B78%3D&reserved=0
> 
> cocci warnings: (new ones prefixed by >>)
> >> drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-
> by-32 division, please consider using div64_ul instead.
> 
> vim +404 drivers/clk/clk-versaclock3.c
> 
> 6e9aff555db7b6 Biju Das 2023-07-05  382
> 6e9aff555db7b6 Biju Das 2023-07-05  383  static long
> vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> 6e9aff555db7b6 Biju Das 2023-07-05  384  			       unsigned
> long *parent_rate)
> 6e9aff555db7b6 Biju Das 2023-07-05  385  {
> 6e9aff555db7b6 Biju Das 2023-07-05  386  	struct vc3_hw_data *vc3 =
> container_of(hw, struct vc3_hw_data, hw);
> 6e9aff555db7b6 Biju Das 2023-07-05  387  	const struct vc3_pll_data *pll
> = vc3->data;
> 6e9aff555db7b6 Biju Das 2023-07-05  388  	u64 div_frc;
> 6e9aff555db7b6 Biju Das 2023-07-05  389
> 6e9aff555db7b6 Biju Das 2023-07-05  390  	if (rate < pll->vco_min)
> 6e9aff555db7b6 Biju Das 2023-07-05  391  		rate = pll->vco_min;
> 6e9aff555db7b6 Biju Das 2023-07-05  392  	if (rate > pll->vco_max)
> 6e9aff555db7b6 Biju Das 2023-07-05  393  		rate = pll->vco_max;
> 6e9aff555db7b6 Biju Das 2023-07-05  394
> 6e9aff555db7b6 Biju Das 2023-07-05  395  	vc3->div_int = rate /
> *parent_rate;
> 6e9aff555db7b6 Biju Das 2023-07-05  396
> 6e9aff555db7b6 Biju Das 2023-07-05  397  	if (pll->num == VC3_PLL2) {
> 6e9aff555db7b6 Biju Das 2023-07-05  398  		if (vc3->div_int > 0x7ff)
> 6e9aff555db7b6 Biju Das 2023-07-05  399  			rate = *parent_rate
> * 0x7ff;
> 6e9aff555db7b6 Biju Das 2023-07-05  400
> 6e9aff555db7b6 Biju Das 2023-07-05  401  		/* Determine best
> fractional part, which is 16 bit wide */
> 6e9aff555db7b6 Biju Das 2023-07-05  402  		div_frc = rate %
> *parent_rate;
> 6e9aff555db7b6 Biju Das 2023-07-05  403  		div_frc *= BIT(16) - 1;
> 6e9aff555db7b6 Biju Das 2023-07-05 @404  		do_div(div_frc,
> *parent_rate);
> 6e9aff555db7b6 Biju Das 2023-07-05  405
> 6e9aff555db7b6 Biju Das 2023-07-05  406  		vc3->div_frc =
> (u32)div_frc;
> 6e9aff555db7b6 Biju Das 2023-07-05  407  		rate = (*parent_rate *
> 6e9aff555db7b6 Biju Das 2023-07-05  408  			(vc3->div_int *
> VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
> 6e9aff555db7b6 Biju Das 2023-07-05  409  	} else {
> 6e9aff555db7b6 Biju Das 2023-07-05  410  		rate = *parent_rate *
> vc3->div_int;
> 6e9aff555db7b6 Biju Das 2023-07-05  411  	}
> 6e9aff555db7b6 Biju Das 2023-07-05  412
> 6e9aff555db7b6 Biju Das 2023-07-05  413  	return rate;
> 6e9aff555db7b6 Biju Das 2023-07-05  414  }
> 6e9aff555db7b6 Biju Das 2023-07-05  415
> 
> --
> 0-DAY CI Kernel Test Service


^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd)
  2023-07-27  8:34 ` Biju Das
@ 2023-07-27  8:43   ` Julia Lawall
  2023-07-27  9:19     ` Biju Das
  0 siblings, 1 reply; 6+ messages in thread
From: Julia Lawall @ 2023-07-27  8:43 UTC (permalink / raw)
  To: Biju Das; +Cc: Linux Memory Management List, Stephen Boyd, oe-kbuild-all



On Thu, 27 Jul 2023, Biju Das wrote:

> Hi,
>
> The reproduce link is not working for me.
>
> https://download.01.org/0day-ci/archive/20230727/202307270841.yr5HxYIl-lkp@intel.com/reproduce
>
> Can you please provide instruction to reproduce this issue?

I don't think it's intended to be reproduced.  The issue is just that a
long value is being passed to an integer that is 32 bit.  If the long
value will never be very big, then you can just ignore the warning.

julia

>
> Cheers,
> Biju
>
> > versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division,
> > please consider using div64_ul instead. (fwd)
> >
> >
> >
> > ---------- Forwarded message ----------
> > Date: Thu, 27 Jul 2023 08:50:37 +0800
> > From: kernel test robot <lkp@intel.com>
> > To: oe-kbuild@lists.linux.dev
> > Cc: lkp@intel.com, Julia Lawall <julia.lawall@inria.fr>
> > Subject: [linux-next:master 2742/4710] drivers/clk/clk-
> > versaclock3.c:404:2-8:
> >     WARNING: do_div() does a 64-by-32 division,
> >     please consider using div64_ul instead.
> >
> > BCC: lkp@intel.com
> > CC: oe-kbuild-all@lists.linux.dev
> > CC: Linux Memory Management List <linux-mm@kvack.org>
> > TO: Biju Das <biju.das.jz@bp.renesas.com>
> > CC: Stephen Boyd <sboyd@kernel.org>
> >
> > tree:
> >
> > If you fix the issue in a separate patch/commit (i.e. not just a new
> > version of the same patch/commit), kindly add following tags
> > | Reported-by: kernel test robot <lkp@intel.com>
> > | Reported-by: Julia Lawall <julia.lawall@inria.fr>
> > | Closes:
> %2BsY49B78%3D&reserved=0
> >
> > cocci warnings: (new ones prefixed by >>)
> > >> drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-
> > by-32 division, please consider using div64_ul instead.
> >
> > vim +404 drivers/clk/clk-versaclock3.c
> >
> > 6e9aff555db7b6 Biju Das 2023-07-05  382
> > 6e9aff555db7b6 Biju Das 2023-07-05  383  static long
> > vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > 6e9aff555db7b6 Biju Das 2023-07-05  384  			       unsigned
> > long *parent_rate)
> > 6e9aff555db7b6 Biju Das 2023-07-05  385  {
> > 6e9aff555db7b6 Biju Das 2023-07-05  386  	struct vc3_hw_data *vc3 =
> > container_of(hw, struct vc3_hw_data, hw);
> > 6e9aff555db7b6 Biju Das 2023-07-05  387  	const struct vc3_pll_data *pll
> > = vc3->data;
> > 6e9aff555db7b6 Biju Das 2023-07-05  388  	u64 div_frc;
> > 6e9aff555db7b6 Biju Das 2023-07-05  389
> > 6e9aff555db7b6 Biju Das 2023-07-05  390  	if (rate < pll->vco_min)
> > 6e9aff555db7b6 Biju Das 2023-07-05  391  		rate = pll->vco_min;
> > 6e9aff555db7b6 Biju Das 2023-07-05  392  	if (rate > pll->vco_max)
> > 6e9aff555db7b6 Biju Das 2023-07-05  393  		rate = pll->vco_max;
> > 6e9aff555db7b6 Biju Das 2023-07-05  394
> > 6e9aff555db7b6 Biju Das 2023-07-05  395  	vc3->div_int = rate /
> > *parent_rate;
> > 6e9aff555db7b6 Biju Das 2023-07-05  396
> > 6e9aff555db7b6 Biju Das 2023-07-05  397  	if (pll->num == VC3_PLL2) {
> > 6e9aff555db7b6 Biju Das 2023-07-05  398  		if (vc3->div_int > 0x7ff)
> > 6e9aff555db7b6 Biju Das 2023-07-05  399  			rate = *parent_rate
> > * 0x7ff;
> > 6e9aff555db7b6 Biju Das 2023-07-05  400
> > 6e9aff555db7b6 Biju Das 2023-07-05  401  		/* Determine best
> > fractional part, which is 16 bit wide */
> > 6e9aff555db7b6 Biju Das 2023-07-05  402  		div_frc = rate %
> > *parent_rate;
> > 6e9aff555db7b6 Biju Das 2023-07-05  403  		div_frc *= BIT(16) - 1;
> > 6e9aff555db7b6 Biju Das 2023-07-05 @404  		do_div(div_frc,
> > *parent_rate);
> > 6e9aff555db7b6 Biju Das 2023-07-05  405
> > 6e9aff555db7b6 Biju Das 2023-07-05  406  		vc3->div_frc =
> > (u32)div_frc;
> > 6e9aff555db7b6 Biju Das 2023-07-05  407  		rate = (*parent_rate *
> > 6e9aff555db7b6 Biju Das 2023-07-05  408  			(vc3->div_int *
> > VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
> > 6e9aff555db7b6 Biju Das 2023-07-05  409  	} else {
> > 6e9aff555db7b6 Biju Das 2023-07-05  410  		rate = *parent_rate *
> > vc3->div_int;
> > 6e9aff555db7b6 Biju Das 2023-07-05  411  	}
> > 6e9aff555db7b6 Biju Das 2023-07-05  412
> > 6e9aff555db7b6 Biju Das 2023-07-05  413  	return rate;
> > 6e9aff555db7b6 Biju Das 2023-07-05  414  }
> > 6e9aff555db7b6 Biju Das 2023-07-05  415
> >
> > --
> > 0-DAY CI Kernel Test Service
>


^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd)
  2023-07-27  8:43   ` Julia Lawall
@ 2023-07-27  9:19     ` Biju Das
  2023-07-27  9:25       ` Geert Uytterhoeven
  0 siblings, 1 reply; 6+ messages in thread
From: Biju Das @ 2023-07-27  9:19 UTC (permalink / raw)
  To: Julia Lawall
  Cc: Linux Memory Management List, Stephen Boyd, oe-kbuild-all,
	Geert Uytterhoeven, linux-renesas-soc

Hi Julia,

> versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please
> consider using div64_ul instead. (fwd)
> 
> 
> 
> On Thu, 27 Jul 2023, Biju Das wrote:
> 
> > Hi,
> >
> > The reproduce link is not working for me.
> >
> >
> > Can you please provide instruction to reproduce this issue?
> 
> I don't think it's intended to be reproduced.  The issue is just that a
> long value is being passed to an integer that is 32 bit.  If the long
> value will never be very big, then you can just ignore the warning.

The rate values are well below max 32 bit, 4294967296. So I guess, it is ok.

xtal                                 0        0        0    24000000          0     0  50000         Y
    ref                               0        0        0    24000000          0     0  50000         Y
    pfd1                              0        0        0    24000000          0     0  50000         Y
       pll1                           0        0        0   600000000          0     0  50000         Y
          div2                        0        0        0    12000000          0     0  50000         Y
             se3_mux                  0        0        0    12000000          0     0  50000         Y
                se3                   0        0        0    12000000          0     0  50000         Y
          div1_mux                    0        0        0   600000000          0     0  50000         Y
             div1                     0        0        0    25000000          0     0  50000         Y
                diff1_mux             0        0        0    25000000          0     0  50000         Y
                   diff1              0        0        0    25000000          0     0  50000         Y
    pfd3_mux                          0        0        0    24000000          0     0  50000         Y
       pfd3                           0        0        0      960000          0     0  50000         Y
          pll3                        0        0        0   564480000          0     0  50000         Y
             div5                     0        0        0    11289600          0     0  50000         Y
                se1_mux               0        0        0    11289600          0     0  50000         Y
                   se1                0        0        0    11289600          0     0  50000         Y
                se2_mux               0        0        0    11289600          0     0  50000         Y
                   se2                0        0        0    11289600          0     0  50000         Y
    pfd2_mux                          0        0        0    24000000          0     0  50000         Y
       pfd2                           0        0        0    24000000          0     0  50000         Y
          pll2                        0        0        0   491519897          0     0  50000         Y
             div4_mux                 0        0        0   491519897          0     0  50000         Y
                div4                  0        0        0    12287998          0     0  50000         Y
             div3_mux                 0        0        0   491519897          0     0  50000         Y
                div3                  0        0        0    12287998          0     0  50000         Y
                   diff2_mux          0        0        0    12287998          0     0  50000         Y
                      diff2           0        0        0    12287998          0     0  50000         Y


Cheers,
Biju

> >
> > > versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division,
> > > please consider using div64_ul instead. (fwd)
> > >
> > >
> > >
> > > ---------- Forwarded message ----------
> > > Date: Thu, 27 Jul 2023 08:50:37 +0800
> > > From: kernel test robot <lkp@intel.com>
> > > To: oe-kbuild@lists.linux.dev
> > > Cc: lkp@intel.com, Julia Lawall <julia.lawall@inria.fr>
> > > Subject: [linux-next:master 2742/4710] drivers/clk/clk-
> > > versaclock3.c:404:2-8:
> > >     WARNING: do_div() does a 64-by-32 division,
> > >     please consider using div64_ul instead.
> > >
> > > BCC: lkp@intel.com
> > > CC: oe-kbuild-all@lists.linux.dev
> > > CC: Linux Memory Management List <linux-mm@kvack.org>
> > > TO: Biju Das <biju.das.jz@bp.renesas.com>
> > > CC: Stephen Boyd <sboyd@kernel.org>
> > >
> > > tree:
> > >
> > > If you fix the issue in a separate patch/commit (i.e. not just a new
> > > version of the same patch/commit), kindly add following tags
> > > | Reported-by: kernel test robot <lkp@intel.com>
> > > | Reported-by: Julia Lawall <julia.lawall@inria.fr>
> > > | Closes:
> > %2BsY49B78%3D&reserved=0
> > >
> > > cocci warnings: (new ones prefixed by >>)
> > > >> drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a
> > > >> 64-
> > > by-32 division, please consider using div64_ul instead.
> > >
> > > vim +404 drivers/clk/clk-versaclock3.c
> > >
> > > 6e9aff555db7b6 Biju Das 2023-07-05  382
> > > 6e9aff555db7b6 Biju Das 2023-07-05  383  static long
> > > vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > > 6e9aff555db7b6 Biju Das 2023-07-05  384
> unsigned
> > > long *parent_rate)
> > > 6e9aff555db7b6 Biju Das 2023-07-05  385  {
> > > 6e9aff555db7b6 Biju Das 2023-07-05  386  	struct vc3_hw_data *vc3 =
> > > container_of(hw, struct vc3_hw_data, hw);
> > > 6e9aff555db7b6 Biju Das 2023-07-05  387  	const struct vc3_pll_data
> *pll
> > > = vc3->data;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  388  	u64 div_frc;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  389
> > > 6e9aff555db7b6 Biju Das 2023-07-05  390  	if (rate < pll->vco_min)
> > > 6e9aff555db7b6 Biju Das 2023-07-05  391  		rate = pll->vco_min;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  392  	if (rate > pll->vco_max)
> > > 6e9aff555db7b6 Biju Das 2023-07-05  393  		rate = pll->vco_max;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  394
> > > 6e9aff555db7b6 Biju Das 2023-07-05  395  	vc3->div_int = rate /
> > > *parent_rate;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  396
> > > 6e9aff555db7b6 Biju Das 2023-07-05  397  	if (pll->num == VC3_PLL2)
> {
> > > 6e9aff555db7b6 Biju Das 2023-07-05  398  		if (vc3->div_int >
> 0x7ff)
> > > 6e9aff555db7b6 Biju Das 2023-07-05  399  			rate =
> *parent_rate
> > > * 0x7ff;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  400
> > > 6e9aff555db7b6 Biju Das 2023-07-05  401  		/* Determine best
> > > fractional part, which is 16 bit wide */
> > > 6e9aff555db7b6 Biju Das 2023-07-05  402  		div_frc = rate %
> > > *parent_rate;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  403  		div_frc *= BIT(16) -
> 1;
> > > 6e9aff555db7b6 Biju Das 2023-07-05 @404  		do_div(div_frc,
> > > *parent_rate);
> > > 6e9aff555db7b6 Biju Das 2023-07-05  405
> > > 6e9aff555db7b6 Biju Das 2023-07-05  406  		vc3->div_frc =
> > > (u32)div_frc;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  407  		rate = (*parent_rate
> *
> > > 6e9aff555db7b6 Biju Das 2023-07-05  408  			(vc3->div_int
> *
> > > VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
> > > 6e9aff555db7b6 Biju Das 2023-07-05  409  	} else {
> > > 6e9aff555db7b6 Biju Das 2023-07-05  410  		rate = *parent_rate
> *
> > > vc3->div_int;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  411  	}
> > > 6e9aff555db7b6 Biju Das 2023-07-05  412
> > > 6e9aff555db7b6 Biju Das 2023-07-05  413  	return rate;
> > > 6e9aff555db7b6 Biju Das 2023-07-05  414  }
> > > 6e9aff555db7b6 Biju Das 2023-07-05  415
> > >
> > > --
> > > 0-DAY CI Kernel Test Service
> >


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd)
  2023-07-27  9:19     ` Biju Das
@ 2023-07-27  9:25       ` Geert Uytterhoeven
  2023-07-27 10:01         ` Biju Das
  0 siblings, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2023-07-27  9:25 UTC (permalink / raw)
  To: Biju Das
  Cc: Julia Lawall, Linux Memory Management List, Stephen Boyd,
	oe-kbuild-all, Geert Uytterhoeven, linux-renesas-soc

Hi Biju,

On Thu, Jul 27, 2023 at 11:19 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please
> > consider using div64_ul instead. (fwd)
> >
> > On Thu, 27 Jul 2023, Biju Das wrote:
> > > The reproduce link is not working for me.
> > >
> > > Can you please provide instruction to reproduce this issue?
> >
> > I don't think it's intended to be reproduced.  The issue is just that a
> > long value is being passed to an integer that is 32 bit.  If the long
> > value will never be very big, then you can just ignore the warning.
>
> The rate values are well below max 32 bit, 4294967296. So I guess, it is ok.

The type of the parent_rate in/output parameter of clk_ops.round_rate()
is unsigned long.  Hence you should use div64_ul().

> > > > versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division,
> > > > please consider using div64_ul instead. (fwd)
> > > >
> > > >
> > > >
> > > > ---------- Forwarded message ----------
> > > > Date: Thu, 27 Jul 2023 08:50:37 +0800
> > > > From: kernel test robot <lkp@intel.com>
> > > > To: oe-kbuild@lists.linux.dev
> > > > Cc: lkp@intel.com, Julia Lawall <julia.lawall@inria.fr>
> > > > Subject: [linux-next:master 2742/4710] drivers/clk/clk-
> > > > versaclock3.c:404:2-8:
> > > >     WARNING: do_div() does a 64-by-32 division,
> > > >     please consider using div64_ul instead.
> > > >
> > > > BCC: lkp@intel.com
> > > > CC: oe-kbuild-all@lists.linux.dev
> > > > CC: Linux Memory Management List <linux-mm@kvack.org>
> > > > TO: Biju Das <biju.das.jz@bp.renesas.com>
> > > > CC: Stephen Boyd <sboyd@kernel.org>
> > > >
> > > > tree:
> > > >
> > > > If you fix the issue in a separate patch/commit (i.e. not just a new
> > > > version of the same patch/commit), kindly add following tags
> > > > | Reported-by: kernel test robot <lkp@intel.com>
> > > > | Reported-by: Julia Lawall <julia.lawall@inria.fr>
> > > > | Closes:
> > > %2BsY49B78%3D&reserved=0
> > > >
> > > > cocci warnings: (new ones prefixed by >>)
> > > > >> drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a
> > > > >> 64-
> > > > by-32 division, please consider using div64_ul instead.
> > > >
> > > > vim +404 drivers/clk/clk-versaclock3.c
> > > >
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  382
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  383  static long
> > > > vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  384
> > unsigned
> > > > long *parent_rate)
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  385  {
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  386   struct vc3_hw_data *vc3 =
> > > > container_of(hw, struct vc3_hw_data, hw);
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  387   const struct vc3_pll_data
> > *pll
> > > > = vc3->data;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  388   u64 div_frc;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  389
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  390   if (rate < pll->vco_min)
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  391           rate = pll->vco_min;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  392   if (rate > pll->vco_max)
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  393           rate = pll->vco_max;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  394
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  395   vc3->div_int = rate /
> > > > *parent_rate;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  396
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  397   if (pll->num == VC3_PLL2)
> > {
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  398           if (vc3->div_int >
> > 0x7ff)
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  399                   rate =
> > *parent_rate
> > > > * 0x7ff;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  400
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  401           /* Determine best
> > > > fractional part, which is 16 bit wide */
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  402           div_frc = rate %
> > > > *parent_rate;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  403           div_frc *= BIT(16) -
> > 1;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05 @404           do_div(div_frc,
> > > > *parent_rate);
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  405
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  406           vc3->div_frc =
> > > > (u32)div_frc;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  407           rate = (*parent_rate
> > *
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  408                   (vc3->div_int
> > *
> > > > VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  409   } else {
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  410           rate = *parent_rate
> > *
> > > > vc3->div_int;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  411   }
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  412
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  413   return rate;
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  414  }
> > > > 6e9aff555db7b6 Biju Das 2023-07-05  415
> > > >
> > > > --
> > > > 0-DAY CI Kernel Test Service
> > >



-- 
Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd)
  2023-07-27  9:25       ` Geert Uytterhoeven
@ 2023-07-27 10:01         ` Biju Das
  0 siblings, 0 replies; 6+ messages in thread
From: Biju Das @ 2023-07-27 10:01 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Julia Lawall, Linux Memory Management List, Stephen Boyd,
	oe-kbuild-all, Geert Uytterhoeven, linux-renesas-soc

Hi Geert,

Thanks for the feedback.

> Subject: Re: [linux-next:master 2742/4710] drivers/clk/clk-
> versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please
> consider using div64_ul instead. (fwd)
> 
> Hi Biju,
> 
> On Thu, Jul 27, 2023 at 11:19 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division,
> > > please consider using div64_ul instead. (fwd)
> > >
> > > On Thu, 27 Jul 2023, Biju Das wrote:
> > > > The reproduce link is not working for me.
> > > >
> > > > Can you please provide instruction to reproduce this issue?
> > >
> > > I don't think it's intended to be reproduced.  The issue is just
> > > that a long value is being passed to an integer that is 32 bit.  If
> > > the long value will never be very big, then you can just ignore the
> warning.
> >
> > The rate values are well below max 32 bit, 4294967296. So I guess, it is
> ok.
> 
> The type of the parent_rate in/output parameter of clk_ops.round_rate() is
> unsigned long.  Hence you should use div64_ul().

Agreed. Will send a patch to fix this issue.

Cheers,
Biju

> > > > > versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32
> > > > > division, please consider using div64_ul instead. (fwd)
> > > > >
> > > > >
> > > > >
> > > > > ---------- Forwarded message ----------
> > > > > Date: Thu, 27 Jul 2023 08:50:37 +0800
> > > > > From: kernel test robot <lkp@intel.com>
> > > > > To: oe-kbuild@lists.linux.dev
> > > > > Cc: lkp@intel.com, Julia Lawall <julia.lawall@inria.fr>
> > > > > Subject: [linux-next:master 2742/4710] drivers/clk/clk-
> > > > > versaclock3.c:404:2-8:
> > > > >     WARNING: do_div() does a 64-by-32 division,
> > > > >     please consider using div64_ul instead.
> > > > >
> > > > > BCC: lkp@intel.com
> > > > > CC: oe-kbuild-all@lists.linux.dev
> > > > > CC: Linux Memory Management List <linux-mm@kvack.org>
> > > > > TO: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > CC: Stephen Boyd <sboyd@kernel.org>
> > > > >
> > > > > tree:
> > > > >
> > > > > If you fix the issue in a separate patch/commit (i.e. not just a
> > > > > new version of the same patch/commit), kindly add following tags
> > > > > | Reported-by: kernel test robot <lkp@intel.com>
> > > > > | Reported-by: Julia Lawall <julia.lawall@inria.fr>
> > > > > | Closes:
> > > > %2BsY49B78%3D&reserved=0
> > > > >
> > > > > cocci warnings: (new ones prefixed by >>)
> > > > > >> drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does
> > > > > >> a
> > > > > >> 64-
> > > > > by-32 division, please consider using div64_ul instead.
> > > > >
> > > > > vim +404 drivers/clk/clk-versaclock3.c
> > > > >
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  382
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  383  static long
> > > > > vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  384
> > > unsigned
> > > > > long *parent_rate)
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  385  {
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  386   struct vc3_hw_data *vc3
> =
> > > > > container_of(hw, struct vc3_hw_data, hw);
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  387   const struct
> vc3_pll_data
> > > *pll
> > > > > = vc3->data;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  388   u64 div_frc;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  389
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  390   if (rate < pll->vco_min)
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  391           rate = pll-
> >vco_min;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  392   if (rate > pll->vco_max)
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  393           rate = pll-
> >vco_max;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  394
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  395   vc3->div_int = rate /
> > > > > *parent_rate;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  396
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  397   if (pll->num ==
> VC3_PLL2)
> > > {
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  398           if (vc3->div_int
> >
> > > 0x7ff)
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  399                   rate =
> > > *parent_rate
> > > > > * 0x7ff;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  400
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  401           /* Determine
> best
> > > > > fractional part, which is 16 bit wide */
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  402           div_frc = rate %
> > > > > *parent_rate;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  403           div_frc *=
> BIT(16) -
> > > 1;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05 @404           do_div(div_frc,
> > > > > *parent_rate);
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  405
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  406           vc3->div_frc =
> > > > > (u32)div_frc;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  407           rate =
> (*parent_rate
> > > *
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  408                   (vc3-
> >div_int
> > > *
> > > > > VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  409   } else {
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  410           rate =
> *parent_rate
> > > *
> > > > > vc3->div_int;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  411   }
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  412
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  413   return rate;
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  414  }
> > > > > 6e9aff555db7b6 Biju Das 2023-07-05  415
> > > > >
> > > > > --
> > > > > 0-DAY CI Kernel Test Service
> > > >
> 
> 
> 
> --
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2023-07-27 10:01 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-27  5:10 [linux-next:master 2742/4710] drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. (fwd) Julia Lawall
2023-07-27  8:34 ` Biju Das
2023-07-27  8:43   ` Julia Lawall
2023-07-27  9:19     ` Biju Das
2023-07-27  9:25       ` Geert Uytterhoeven
2023-07-27 10:01         ` Biju Das

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