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From: Icenowy Zheng <uwu@icenowy.me>
To: Robin Murphy <robin.murphy@arm.com>,
	"Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
	Jisheng Zhang <jszhang@kernel.org>
Cc: "Drew Fustini" <dfustini@baylibre.com>,
	"Christoph Hellwig" <hch@lst.de>,
	"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"Robert Nelson" <robertcnelson@gmail.com>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Adrian Hunter" <adrian.hunter@intel.com>,
	"Guo Ren" <guoren@kernel.org>, "Fu Wei" <wefu@redhat.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Conor Dooley" <conor@kernel.org>,
	"Jason Kridner" <jkridner@beagleboard.org>,
	"Xi Ruoyao" <xry111@xry111.site>, "Han Gao" <gaohan@iscas.ac.cn>,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Björn Töpel" <bjorn@kernel.org>,
	"Alexandre Ghiti" <alexghiti@rivosinc.com>,
	Linux-MM <linux-mm@kvack.org>
Subject: Re: [PATCH 0/6] RISC-V: Add eMMC support for TH1520 boards
Date: Wed, 04 Oct 2023 22:46:49 +0800	[thread overview]
Message-ID: <be4e43b676ca5619e99b0f5abf228e45fadedb70.camel@icenowy.me> (raw)
In-Reply-To: <a568a9dd-bab2-1e23-c4d5-9f6475bdcc3b@arm.com>

在 2023-10-04星期三的 15:18 +0100,Robin Murphy写道:
> On 04/10/2023 3:02 pm, Icenowy Zheng wrote:
> [...]
> > > > > I believe commit 484861e09f3e ("soc: renesas: Kconfig: Select
> > > > > the
> > > > > required configs for RZ/Five SoC") can cause regression on
> > > > > all
> > > > > non-dma-coherent riscv platforms with generic defconfig. This
> > > > > is
> > > > > a common issue. The logic here is: generic riscv defconfig
> > > > > selects
> > > > > ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes
> > > > > all
> > > > > non-dma-coherent riscv platforms have a dma global pool, this
> > > > > assumption
> > > > > seems not correct. And I believe DMA_GLOBAL_POOL should not
> > > > > be
> > > > > selected by ARCH_SOCFAMILIY, instead, only ARCH under some
> > > > > specific
> > > > > conditions can select it globaly, for example NOMMU ARM and
> > > > > so
> > > > > on.
> > > > > 
> > > > > Since this is a regression, what's proper fix? any suggestion
> > > > > is
> > > > > appreciated.
> > > 
> > > I think the answer is to not select DMA_GLOBAL_POOL, since that
> > > is
> > > only
> > 
> > Well I think for RISC-V, it's not NOMMU only but applicable for
> > every
> > core that does not support Svpbmt or vendor-specific alternatives,
> > because the original RISC-V priv spec does not define memory
> > attributes
> > in page table entries.
> > 
> > For the Renesas/Andes case I think a pool is set by OpenSBI with
> > vendor-specific M-mode facility and then passed in DT, and the S-
> > mode
> > (which MMU is enabled in) just sees fixed memory attributes, in
> > this
> > case I think DMA_GLOBAL_POOL is needed.
> 
> Oh wow, is that really a thing? In that case, either you just can't 
> support this platform in a multi-platform kernel, or someone needs to
> do 

Emmmm thus RZ/Five should `depends on NONPORTABLE`?

> some fiddly work in dma-direct to a) introduce the notion of an
> optional 
> global pool, and b) make it somehow cope with DMA_DIRECT_REMAP being 
> enabled but non-functional.
> 
> Thanks,
> Robin.



  reply	other threads:[~2023-10-04 14:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20230921-th1520-mmc-v1-0-49f76c274fb3@baylibre.com>
     [not found] ` <CAOCHtYhnx1EpBM+o3xhdsicx5uqLidojK3f0HQ+VfyVv1ZXnVQ@mail.gmail.com>
     [not found]   ` <CAOCHtYi5Ab5ppCmaQV3QuKQcpmJX+sHdAmtuEXhfq8xf5fFCYQ@mail.gmail.com>
     [not found]     ` <ZRuamJuShOnvP1pr@x1>
     [not found]       ` <ZR1M3FcdXrDmIGu2@xhacker>
2023-10-04 13:02         ` Lad, Prabhakar
2023-10-04 13:49           ` Robin Murphy
2023-10-04 14:02             ` Icenowy Zheng
2023-10-04 14:18               ` Robin Murphy
2023-10-04 14:46                 ` Icenowy Zheng [this message]
2023-10-04 14:58                 ` Icenowy Zheng
2023-10-04 16:03                 ` Lad, Prabhakar
2023-10-04 17:16                   ` Lad, Prabhakar
2023-10-04 18:49                     ` Samuel Holland
2023-10-04 19:38                       ` Robin Murphy
2023-10-04 20:47                         ` Lad, Prabhakar
2023-10-05  6:57                     ` Christoph Hellwig
2023-10-04 14:06             ` Jisheng Zhang
2023-10-04 15:27               ` Geert Uytterhoeven

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