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Sat, 9 Sep 2023 16:11:57 -0400 (EDT) Message-ID: Date: Sat, 9 Sep 2023 15:11:56 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux ppc64le; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v3 0/4] riscv: tlb flush improvements Content-Language: en-US To: Alexandre Ghiti References: <20230801085402.1168351-1-alexghiti@rivosinc.com> Cc: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Samuel Holland In-Reply-To: <20230801085402.1168351-1-alexghiti@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: 7AA6120020 X-Rspam-User: X-Rspamd-Server: rspam04 X-Stat-Signature: 1rbpmtm3or5yq5fg4ya8e5u4z58jib8y X-HE-Tag: 1694290322-996092 X-HE-Meta: U2FsdGVkX1/4Wk/IZx+ApNgc2vGeB1EER/tm0FL3QXt7VIAzqSebGy75QjhIJeZ54+9r3QTJ7LNJ91Sd0YWw5xNMGMQbZ5q7pcNNhEwMBJMUNBirY9hZHfYH3BIB1L+sYqARk98y0GiNec9Y/UfCpmrhBKUyKSemnTqlaub30WjHgZvXsIGCGlj/ylnhvlB7Lade79ONRHlzJJAwLXGzvsdFr7FN7ly/Qcg4S+iIOGmwgYh3geVJOwdOngmunuRHJb467y5PIf5+LpdLBjpW9QgiKCJ/bgYgPymP5oSbxTiwmA4xDROwe6H4uO8eRRZ0aNAVovfPNHR21qPPlrGGD8YRwX+ZAHEjOLDGGG+zdVYZ3nRcqkLzCKRO3E2aDgDzseUjRkg3ioeb648Kq9KsCHfhykiZ40OMEVdsL1prEfZQhgGPzJHXmL8CvGtZB0Iv3ZPU/tb3sOxmDiEJcRJZiiNqoOd7P57CMgpoEvpPj/LAEhqTq1E9h6mtewj2pd4ypTZq2h49k0s4dx0BVCRhYFgSV/tsyJth/BcwusyT4pBTG0im7dHvVGWdZuqdyWHHGNL7wMaweVIuB0i4LH7l3Z87ejTV4PppbfyHqA+xrD2TUHso7vP1pT8Y9ZlBtqdtq/TLxKxSJCce++uhyNeGxZvQQUS9QFLARbApcr0kIBx6JiatmovnYjQMcpvpzym9qWmbt1wJcebJ3mi6tvYuAl7fogZslgJ4u4zyAj0sm08APRdr6CYXbj14SwrOVsy7pz5nvInljZzzjfq09Y08lGpx+TAVCgA7O/NTXE8CBiUSx9OknMQp1nS4HWTbv9erWUTBZ2e8fpG2IClDjqg2U5bTiDxdPPR+GgZ7NQVB5qHvdTm+XwnOzHXLfz55bY5r64dBEncp4NM0exoYvNhSs2DeJzFDiWdTTyAcygw8vMAqL2gg5OeP1YHV8Hj8rR7OC5Vm8e0YMH4SAUEFBXd nDUyevyJ TIzAfWi1aSNLXyRsbZW9Ks2EyvhKr44ITb/KgdN+vuHCC1nB/Pk/H2uFZhBd16FI/sPF1mwWJ/I7LT2XE6QQQX1b6ynQF1TnPHQkmiXYPJHnqLOGzb75wb00ud3HqO+mEKZ5Fb/8NDJe/lEmsH+Gjvh3ia2nFF1YpxtL9RCW7Jgs+x8FLZc/tLaL9/1209YeVrURG0Qd3LVRbGaUdfp0wrS+Hckldn83UvsMRo7Hr6u5QIRkMWIigmWcJS8MqhIp1J/5P0LLMIC4FEQOG3LxXHOjp9VU1ILG1QshqbBMVvY08z03/lHsbQC8GxUfoEm5l4dQORxRFo/p+/cO0jQJ6r/LIsAvFo+tW7vGsEJA3l2ovTRw= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 8/1/23 03:53, Alexandre Ghiti wrote: > This series optimizes the tlb flushes on riscv which used to simply > flush the whole tlb whatever the size of the range to flush or the size > of the stride. > > Patch 3 introduces a threshold that is microarchitecture specific and > will very likely be modified by vendors, not sure though which mechanism > we'll use to do that (dt? alternatives? vendor initialization code?). Certainly we would want to set the threshold to zero on SiFive platforms affected by CIP-1200, since they cannot use address-based sfence.vma at all. At least this case could be handled in the existing errata patch function. I don't know about other platforms. Regards, Samuel > > Next steps would be to implement: > - svinval extension as Mayuresh did here [1] > - BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land) > - MMU_GATHER_RCU_TABLE_FREE > - MMU_GATHER_MERGE_VMAS > > Any other idea welcome. > > [1] https://lore.kernel.org/linux-riscv/20230623123849.1425805-1-mchitale@ventanamicro.com/ > > Changes in v3: > - Add RB from Andrew, thanks! > - Unwrap a few lines, as suggested by Andrew > - Introduce defines for -1 constants used in tlbflush.c, as suggested by Andrew and Conor > - Use huge_page_size() directly instead of using the shift, as suggested by Andrew > - Remove misleading comments as suggested by Conor > > Changes in v2: > - Make static tlb_flush_all_threshold, we'll figure out later how to > override this value on a vendor basis, as suggested by Conor and Palmer > - Fix nommu build, as reported by Conor > > Alexandre Ghiti (4): > riscv: Improve flush_tlb() > riscv: Improve flush_tlb_range() for hugetlb pages > riscv: Make __flush_tlb_range() loop over pte instead of flushing the > whole tlb > riscv: Improve flush_tlb_kernel_range() > > arch/riscv/include/asm/tlb.h | 8 ++- > arch/riscv/include/asm/tlbflush.h | 12 ++-- > arch/riscv/mm/tlbflush.c | 98 ++++++++++++++++++++++++++----- > 3 files changed, 99 insertions(+), 19 deletions(-) >