From: Samuel Holland <samuel@sholland.org>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Will Deacon <will@kernel.org>,
"Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>,
Andrew Morton <akpm@linux-foundation.org>,
Nick Piggin <npiggin@gmail.com>,
Peter Zijlstra <peterz@infradead.org>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
Vincent Chen <vincent.chen@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 0/4] riscv: tlb flush improvements
Date: Sat, 9 Sep 2023 15:11:56 -0500 [thread overview]
Message-ID: <bd7f8612-e9bf-deab-450d-f0cde52cdd1b@sholland.org> (raw)
In-Reply-To: <20230801085402.1168351-1-alexghiti@rivosinc.com>
On 8/1/23 03:53, Alexandre Ghiti wrote:
> This series optimizes the tlb flushes on riscv which used to simply
> flush the whole tlb whatever the size of the range to flush or the size
> of the stride.
>
> Patch 3 introduces a threshold that is microarchitecture specific and
> will very likely be modified by vendors, not sure though which mechanism
> we'll use to do that (dt? alternatives? vendor initialization code?).
Certainly we would want to set the threshold to zero on SiFive platforms
affected by CIP-1200, since they cannot use address-based sfence.vma at
all. At least this case could be handled in the existing errata patch
function. I don't know about other platforms.
Regards,
Samuel
>
> Next steps would be to implement:
> - svinval extension as Mayuresh did here [1]
> - BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land)
> - MMU_GATHER_RCU_TABLE_FREE
> - MMU_GATHER_MERGE_VMAS
>
> Any other idea welcome.
>
> [1] https://lore.kernel.org/linux-riscv/20230623123849.1425805-1-mchitale@ventanamicro.com/
>
> Changes in v3:
> - Add RB from Andrew, thanks!
> - Unwrap a few lines, as suggested by Andrew
> - Introduce defines for -1 constants used in tlbflush.c, as suggested by Andrew and Conor
> - Use huge_page_size() directly instead of using the shift, as suggested by Andrew
> - Remove misleading comments as suggested by Conor
>
> Changes in v2:
> - Make static tlb_flush_all_threshold, we'll figure out later how to
> override this value on a vendor basis, as suggested by Conor and Palmer
> - Fix nommu build, as reported by Conor
>
> Alexandre Ghiti (4):
> riscv: Improve flush_tlb()
> riscv: Improve flush_tlb_range() for hugetlb pages
> riscv: Make __flush_tlb_range() loop over pte instead of flushing the
> whole tlb
> riscv: Improve flush_tlb_kernel_range()
>
> arch/riscv/include/asm/tlb.h | 8 ++-
> arch/riscv/include/asm/tlbflush.h | 12 ++--
> arch/riscv/mm/tlbflush.c | 98 ++++++++++++++++++++++++++-----
> 3 files changed, 99 insertions(+), 19 deletions(-)
>
prev parent reply other threads:[~2023-09-09 20:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-01 8:53 Alexandre Ghiti
2023-08-01 8:53 ` [PATCH v3 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
2023-08-01 8:54 ` [PATCH v3 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
2023-08-01 8:54 ` [PATCH v3 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-08-01 8:54 ` [PATCH v3 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
2023-09-06 11:48 ` Lad, Prabhakar
2023-09-06 12:01 ` Alexandre Ghiti
2023-09-06 12:08 ` Lad, Prabhakar
2023-09-06 12:18 ` Alexandre Ghiti
2023-09-06 12:23 ` Lad, Prabhakar
2023-09-06 12:43 ` Alexandre Ghiti
2023-09-06 13:16 ` Palmer Dabbelt
2023-09-06 13:54 ` Lad, Prabhakar
2023-09-07 9:05 ` Alexandre Ghiti
2023-09-07 10:49 ` Lad, Prabhakar
2023-09-08 12:34 ` Alexandre Ghiti
2023-09-06 20:22 ` Nadav Amit
2023-09-07 13:47 ` Alexandre Ghiti
2023-09-09 19:00 ` Samuel Holland
2023-09-11 8:33 ` Alexandre Ghiti
2023-09-06 13:00 ` [PATCH v3 0/4] riscv: tlb flush improvements patchwork-bot+linux-riscv
2023-09-09 20:11 ` Samuel Holland [this message]
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