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From: Rik van Riel <riel@surriel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
	peterz@infradead.org,  dave.hansen@linux.intel.com,
	zhengqi.arch@bytedance.com, nadav.amit@gmail.com,
		thomas.lendacky@amd.com, kernel-team@meta.com,
	linux-mm@kvack.org, 	akpm@linux-foundation.org,
	jackmanb@google.com, jannh@google.com, 	mhklinux@outlook.com,
	andrew.cooper3@citrix.com, Manali Shukla	 <Manali.Shukla@amd.com>
Subject: Re: [PATCH v11 04/12] x86/mm: get INVLPGB count max from CPUID
Date: Wed, 19 Feb 2025 12:52:56 -0500	[thread overview]
Message-ID: <b749384b7dea020880057359d06d4e9172c7aaec.camel@surriel.com> (raw)
In-Reply-To: <20250219115626.GMZ7XG6s-5ftg1XLoZ@fat_crate.local>

On Wed, 2025-02-19 at 12:56 +0100, Borislav Petkov wrote:
> On Thu, Feb 13, 2025 at 11:13:55AM -0500, Rik van Riel wrote:
> > The CPU advertises the maximum number of pages that can be shot
> > down
> > with one INVLPGB instruction in the CPUID data.
> > 
> > Save that information for later use.
> > 
> > Signed-off-by: Rik van Riel <riel@surriel.com>
> > Tested-by: Manali Shukla <Manali.Shukla@amd.com>
> > Tested-by: Brendan Jackman <jackmanb@google.com>
> > Tested-by: Michael Kelley <mhklinux@outlook.com>
> > ---
> >  arch/x86/Kconfig.cpu               | 5 +++++
> >  arch/x86/include/asm/cpufeatures.h | 1 +
> >  arch/x86/include/asm/tlbflush.h    | 7 +++++++
> >  arch/x86/kernel/cpu/amd.c          | 8 ++++++++
> >  4 files changed, 21 insertions(+)
> > 
> > diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
> > index 2a7279d80460..abe013a1b076 100644
> > --- a/arch/x86/Kconfig.cpu
> > +++ b/arch/x86/Kconfig.cpu
> > @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES
> >  	def_bool y
> >  	depends on IA32_FEAT_CTL
> >  
> > +config X86_BROADCAST_TLB_FLUSH
> > +	def_bool y
> > +	depends on CPU_SUP_AMD && 64BIT
> > +
> >  menuconfig PROCESSOR_SELECT
> >  	bool "Supported processor vendors" if EXPERT
> >  	help
> > @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32
> >  config CPU_SUP_AMD
> >  	default y
> >  	bool "Support AMD processors" if PROCESSOR_SELECT
> > +	select X86_BROADCAST_TLB_FLUSH
> 
> CPU_SUP_AMD selects X86_BROADCAST_TLB_FLUSH which depends on
> CPU_SUP_AMD which
> selects X86_BROADCAST_TLB_FLUSH which depends on CPU_SUP_AMD...
> 
> Why do you really need yet another Kconfig symbol? Just whack
> X86_BROADCAST_TLB_FLUSH - it'll be enabled by default on everything
> anyway.

Dave specifically asked me to do things that way.

> 
> > @@ -1139,6 +1141,12 @@ static void cpu_detect_tlb_amd(struct
> > cpuinfo_x86 *c)
> >  		tlb_lli_2m[ENTRIES] = eax & mask;
> >  
> >  	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
> > +
> > +	/* Max number of pages INVLPGB can invalidate in one shot
> > */
> > +	if (boot_cpu_has(X86_FEATURE_INVLPGB)) {
> > +		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
> > +		invlpgb_count_max = (edx & 0xffff) + 1;
> > +	}
> 
> get_cpu_cap() already reads that leaf. You don't need to do it here
> again.
> 
Should I modify get_cpu_cap() to store
c->x86_capabilities[CPUID_8000_0008_EDX] ?

Currently only the EBX data is stored there,
while invlpgb_count_max comes from EDX.

-- 
All Rights Reversed.


  reply	other threads:[~2025-02-19 17:56 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-13 16:13 [PATCH v11 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-02-13 16:13 ` [PATCH v11 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-02-13 16:13 ` [PATCH v11 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-02-13 16:13 ` [PATCH v11 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-02-14 18:07   ` Dave Hansen
2025-02-19 11:21   ` Borislav Petkov
2025-02-13 16:13 ` [PATCH v11 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-14 18:16   ` Dave Hansen
2025-02-19 11:56   ` Borislav Petkov
2025-02-19 17:52     ` Rik van Riel [this message]
2025-02-19 18:23       ` Borislav Petkov
2025-02-19 19:26       ` Dave Hansen
2025-02-13 16:13 ` [PATCH v11 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-02-14 18:22   ` Dave Hansen
2025-02-18 17:23     ` Rik van Riel
2025-02-19 12:04   ` Borislav Petkov
2025-02-19 17:42     ` Rik van Riel
2025-02-19 19:01       ` Dave Hansen
2025-02-19 19:15         ` Borislav Petkov
2025-02-20  2:49           ` Rik van Riel
2025-02-20 10:23             ` Borislav Petkov
2025-02-13 16:13 ` [PATCH v11 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-14 18:35   ` Dave Hansen
2025-02-14 19:40     ` Peter Zijlstra
2025-02-14 19:55       ` Dave Hansen
2025-02-15  1:25         ` Rik van Riel
2025-02-15  2:08           ` Yosry Ahmed
2025-02-18 18:00             ` Rik van Riel
2025-02-18 22:27               ` Dave Hansen
2025-02-19  1:46                 ` Yosry Ahmed
2025-02-13 16:13 ` [PATCH v11 07/12] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-14 18:57   ` Dave Hansen
2025-02-13 16:13 ` [PATCH v11 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-14 18:51   ` Dave Hansen
2025-02-18 19:31     ` Rik van Riel
2025-02-18 19:46       ` Dave Hansen
2025-02-18 20:06         ` Rik van Riel
2025-02-13 16:14 ` [PATCH v11 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-02-14 19:53   ` Dave Hansen
2025-02-17 13:22     ` Brendan Jackman
2025-02-20 15:25     ` Rik van Riel
2025-02-13 16:14 ` [PATCH v11 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-02-13 16:14 ` [PATCH v11 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-02-13 16:14 ` [PATCH v11 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-02-13 18:31 ` [PATCH v11 00/12] AMD broadcast TLB invalidation Brendan Jackman
2025-02-13 18:38   ` Brendan Jackman
2025-02-13 20:02   ` Rik van Riel
2025-02-14  9:36     ` Peter Zijlstra
2025-02-14  9:54       ` Brendan Jackman

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