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Mon, 20 Apr 2026 19:37:10 +0800 (CST) Received: from kwepemr500001.china.huawei.com (unknown [7.202.194.229]) by mail.maildlp.com (Postfix) with ESMTPS id A1F0D40573; Mon, 20 Apr 2026 19:43:31 +0800 (CST) Received: from [10.174.179.248] (10.174.179.248) by kwepemr500001.china.huawei.com (7.202.194.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 20 Apr 2026 19:43:29 +0800 Message-ID: Date: Mon, 20 Apr 2026 19:43:20 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 2/4] mm/pgtable: Make pfn_pte() filter out huge page attributes To: Will Deacon CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20260228070906.1418911-1-yintirui@huawei.com> <20260228070906.1418911-3-yintirui@huawei.com> From: Yin Tirui In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.174.179.248] X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemr500001.china.huawei.com (7.202.194.229) X-Stat-Signature: t7xw9ujzedru45tdhiwwoo51ruidcrh7 X-Rspam-User: X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 7C48080004 X-HE-Tag: 1776685417-185366 X-HE-Meta: U2FsdGVkX18hNHOuXgAZwwFpTWMA+HHrFScCY4WI90NNFpRoN2p463tYwQGWiDNO0T9HogUsswBqONssxqC062Wc7aYi4wBUXk6c8fLdUAvSVPmL+1sYyXsIM2ydOj0b9OmSXEQ+z/X9zPj8F7ryjNUEuj6/J+nHAKjdxnGKNPOk0xPBuG8T9dU5argg12/6t0KUc1TuRSxGoCHNKNYgAmYZ7DBNA0vGpif2TfyeOVnIlwasJYVJmHNNTd8WfqfPuPRgZWVCf2HFyko/0UKoOrc6FQ7cZRHKRBYfKVbtqekslM6SaYW5xioSD7Y5NfXzTPj6Ce0bk8OGqaE26uRJYY/QW+inVCGcG4grGvxpZi4YrCz3l5kOsmI3i+MzroT5D5XBkXJebX0dUQRdNBT0YBNMCOuhOLf9R9PaAml/blKGlMv0M0c63Vi/nu4EfsfKRZzkUC9r15S7/qnfph+aVkMT0mEveyZPwggHIYvhtHtksckjQR/EDdz3wZoqLtaRf+pMuN0snT/kg9KErujyyBuM60oRbzMIRF+DdBqtMa7pgBDFS1ydp6HLm41VcR6qFxR8tr5egoAyh64O/gWcZ4trIs+V9NjgV17rJSt6VGesyxg4SEvMPxRDlrKeFavS2LPyLM++b4/qYYxNZ+OqeW/97dcI8MdxJxARGB7rZHr/6w/eaq9SbPz6bxZmYmqUfhz81xyUGcIZyBgs0LozHPiFslqhn91Ykrr6LzkNCb80FFJS/cYH0RKqVYTQXkONSc11eUzkNNYSvi+LSOskM1K5RuNcNBX+WdIcieGEgqM9gXRv7Hw1OjI2mLuAF50sW82ttryotUiWeTxr5QjeM6PD1biJYUeIYoH/tY2ztktMPcx3HDVttUTedOUe133MSHrt9oW8nnygsAYACwstvR9VrXF/Qrlc6IKPOGDGhxA768qSb9y0cXJn1gadN1KZfbX7fwgZ/G4XZ7f8Hll HRl8SUg8 vRuDq9p7uvpBLYK2iWfkoA25U8aJjM0FquP5TNrO3Ckh9/mLM4uizkjeMW3bNE1ilgGzCuA4NIAi9TLasC3I8l0odCTdnbNO42uIESm9HZD8xM9ad+scJ27EDzLdayWpfT4zAyvSkYJl3UxOzJTYkE3KwUuj6bpjJCnDGseWp8JxmqowKt/P0/hkvmixb2aE2X/PWQP8V4BF0nNFUXHixKG4ubJoBneeFUl0FZHO7qGoE3rvba/8FKNluIzEPvpq3K1k9ney/01Us3ktiuGj6/yhmT8v4ysbEL8Hbtjbqki8QSG7C4b1jqzRme6gmQkqdUSkghYtJ+TUSap9Ma1qliCrkvhz9c6qKXxBUa2IYp1D3hgyU075bGXAuZBUoFIDam6TjzIHA8+D1WMsKxk29DhO7x9wufV2L7p+apj1enH4My/6iK2rCxVNVCQ== Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Hi Will, On 4/20/2026 4:48 PM, Will Deacon wrote: > On Sat, Feb 28, 2026 at 03:09:04PM +0800, Yin Tirui wrote: >> A fundamental principle of page table type safety is that `pte_t` represents >> the lowest level page table entry and should never carry huge page attributes. >> >> Currently, passing a pgprot with huge page bits (e.g., extracted via >> pmd_pgprot()) into pfn_pte() creates a malformed PTE that retains the huge >> attribute, leading to the necessity of the ugly `pte_clrhuge()` anti-pattern. >> >> Enforce type safety by making `pfn_pte()` inherently filter out huge page >> attributes: >> - On x86: Strip the `_PAGE_PSE` bit. >> - On ARM64: Mask out the block descriptor bits in `PTE_TYPE_MASK` and >> enforce the `PTE_TYPE_PAGE` format. >> - On RISC-V: No changes required, as RISC-V leaf PMDs and PTEs share the >> exact same hardware format and do not use a distinct huge bit. >> >> Signed-off-by: Yin Tirui >> --- >> arch/arm64/include/asm/pgtable.h | 4 +++- >> arch/x86/include/asm/pgtable.h | 4 ++++ >> 2 files changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >> index b3e58735c49b..f2a7a40106d2 100644 >> --- a/arch/arm64/include/asm/pgtable.h >> +++ b/arch/arm64/include/asm/pgtable.h >> @@ -141,7 +141,9 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) >> >> #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) >> #define pfn_pte(pfn,prot) \ >> - __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) >> + __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | \ >> + ((pgprot_val(prot) & ~(PTE_TYPE_MASK & ~PTE_VALID)) | \ >> + (PTE_TYPE_PAGE & ~PTE_VALID))) > Why are you touching arch/arm64? We don't implement pte_clrhuge() afaict. > What does this actually fix? Originally, this patch aimed to ensure that pfn_pte() always returns a PTE without any huge page attributes by embedding the logic of pte_clrhuge() directly into pfn_pte(). However, we found this approach doesn't work well on x86, so we've abandoned this design. Following Matthew Wilcox's suggestion, the current approach is instead to have pmd_pgprot() return a 4K–formatted pgprot_t (i.e., without huge page attributes), and then explicitly add the huge page attributes when constructing a PMD via pfn_pmd(). I've already implemented this in my recent commit: https://github.com/torvalds/linux/commit/5b8ce6d33822dd7776432e03a08fe6d2dedac079 > > Will -- Yin Tirui