From: David Rientjes <rientjes@google.com>
To: "Huang, Ying" <ying.huang@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
Andrea Arcangeli <aarcange@redhat.com>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Andi Kleen <andi.kleen@intel.com>, Jan Kara <jack@suse.cz>,
Michal Hocko <mhocko@suse.com>,
Matthew Wilcox <mawilcox@microsoft.com>,
Hugh Dickins <hughd@google.com>, Minchan Kim <minchan@kernel.org>,
Shaohua Li <shli@fb.com>, Christopher Lameter <cl@linux.com>,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
Punit Agrawal <punit.agrawal@arm.com>,
Anshuman Khandual <khandual@linux.vnet.ibm.com>
Subject: Re: [PATCH -mm] mm, hugetlb: Pass fault address to no page handler
Date: Tue, 15 May 2018 13:03:26 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.1805151303160.5896@chino.kir.corp.google.com> (raw)
In-Reply-To: <20180515005756.28942-1-ying.huang@intel.com>
On Tue, 15 May 2018, Huang, Ying wrote:
> From: Huang Ying <ying.huang@intel.com>
>
> This is to take better advantage of huge page clearing
> optimization (c79b57e462b5d, "mm: hugetlb: clear target sub-page last
> when clearing huge page"). Which will clear to access sub-page last
> to avoid the cache lines of to access sub-page to be evicted when
> clearing other sub-pages. This needs to get the address of the
> sub-page to access, that is, the fault address inside of the huge
> page. So the hugetlb no page fault handler is changed to pass that
> information. This will benefit workloads which don't access the begin
> of the huge page after page fault.
>
> With this patch, the throughput increases ~28.1% in vm-scalability
> anon-w-seq test case with 88 processes on a 2 socket Xeon E5 2699 v4
> system (44 cores, 88 threads). The test case creates 88 processes,
> each process mmap a big anonymous memory area and writes to it from
> the end to the begin. For each process, other processes could be seen
> as other workload which generates heavy cache pressure. At the same
> time, the cache miss rate reduced from ~36.3% to ~25.6%, the
> IPC (instruction per cycle) increased from 0.3 to 0.37, and the time
> spent in user space is reduced ~19.3%
>
> Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
> Cc: Andrea Arcangeli <aarcange@redhat.com>
> Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
> Cc: Andi Kleen <andi.kleen@intel.com>
> Cc: Jan Kara <jack@suse.cz>
> Cc: Michal Hocko <mhocko@suse.com>
> Cc: Matthew Wilcox <mawilcox@microsoft.com>
> Cc: Hugh Dickins <hughd@google.com>
> Cc: Minchan Kim <minchan@kernel.org>
> Cc: Shaohua Li <shli@fb.com>
> Cc: Christopher Lameter <cl@linux.com>
> Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> Cc: Punit Agrawal <punit.agrawal@arm.com>
> Cc: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Acked-by: David Rientjes <rientjes@google.com>
next prev parent reply other threads:[~2018-05-15 20:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-15 0:57 Huang, Ying
2018-05-15 3:25 ` Mike Kravetz
2018-05-15 5:19 ` Huang, Ying
2018-05-15 10:38 ` Kirill A. Shutemov
2018-05-16 0:42 ` Huang, Ying
2018-05-16 8:03 ` Kirill A. Shutemov
2018-05-17 1:39 ` Huang, Ying
2018-05-15 20:03 ` David Rientjes [this message]
2018-05-16 9:12 ` Michal Hocko
2018-05-16 20:04 ` Mike Kravetz
2018-05-17 1:45 ` Huang, Ying
2018-05-17 1:41 ` Huang, Ying
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