From: Sean Christopherson <seanjc@google.com>
To: Ankit Agrawal <ankita@nvidia.com>
Cc: Jason Gunthorpe <jgg@nvidia.com>,
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Subject: Re: [PATCH v6 3/5] kvm: arm64: New memslot flag to indicate cacheable mapping
Date: Fri, 6 Jun 2025 10:57:34 -0700 [thread overview]
Message-ID: <aEMsDsi3DSm1up0G@google.com> (raw)
In-Reply-To: <SA1PR12MB71990A84FDB4350DC02CEC6EB064A@SA1PR12MB7199.namprd12.prod.outlook.com>
On Tue, May 27, 2025, Ankit Agrawal wrote:
> > I thought we agreed not to do this? Sean was strongly against it
> > right?
Yes. NAK, at least for this implementation.
IMO, this has no business being in KVM's uAPI, and it's a mess. KVM x86
unconditionally supports cacheable PFNMAP mappings, yet this:
bool __weak kvm_arch_supports_cacheable_pfnmap(void)
{
return false;
}
if (kvm_arch_supports_cacheable_pfnmap())
valid_flags |= KVM_MEM_ENABLE_CACHEABLE_PFNMAP;
means x86 will disallow KVM_MEM_ENABLE_CACHEABLE_PFNMAP. Which is fine-ish from
a uAPI perspective, as the flag is documented as arm64-only, and we can state that
all other architectures always allow cacheable mappings. But even that is a mess,
because KVM won't _guarantee_ the final mapping is cacheable.
On AMD, there's simply no sane way to force WB (KVM can't override guest PAT,
i.e. the memtype requested/set by the guest's stage-1 page tables).
On Intel, after years of pain, we _finally_ got KVM out of a mess where KVM was
forcing WB for all non-MMIO memory. Only to have to immediately revert and add
KVM_X86_QUIRK_IGNORE_GUEST_PAT because buggy guest drivers were relying on KVM's
behavior :-(
So there's zero chance of this memslot flag ever being supported on x86. Which,
again, is fine for uAPI. But for internal code it's going to be all kinds of
confusing, because kvm_arch_supports_cacheable_pfnmap() is a flat out lie.
And as proposed, the memslot flag also doesn't actually address Oliver's want:
The memslot flag says userspace expects a particular GFN range to guarantee
^^^^^^^^^
Write-Back semantics.
IIUC, what Oliver wants is:
if (mapping_type_noncacheable(vma->vm_page_prot)) {
if (new->flags & KVM_MEM_FORCE_CACHEABLE_PFNMAP)
return -EINVAL;
} else {
if (!kvm_arch_supports_cacheable_pfnmap()))
return -EINVAL;
}
That's at least a bit more palatable, as it doesn't create impossible situations
on x86, e.g. x86 simply doesn't support letting userspace force a cacheable.
And Oliver also stated:
Whether or not FWB is employed for a particular region of IPA space is useful
information for userspace deciding what it needs to do to access guest memory.
The above would only cover half of that, i.e. wouldn't prevent userspace from
getting surprised by a WB mapping. So I think it would need to be this?
if (mapping_type_noncacheable(vma->vm_page_prot) !=
!(new->flags & KVM_MEM_FORCE_CACHEABLE_PFNMAP))
return -EINVAL;
Which I don't hate as much, but I still don't love it, as it's overly specific,
e.g. only helps with PFNMAP memory, and pushes a sanity from userspace into KVM.
Which is another complaint with this uAPI: it effectively assumes/implies PFNMAP is
device memory, but that's simply not true. There are zero guarantees with respect
to what actually lies behind any given PFNMAP. It could be device memory, but
it could also be regular RAM, or something in between.
I would much prefer we have a way userspace query the effective memtype for a
range of memory, either for a VMA or for a KVM mapping, and let _userspace_ do
whatever sanity checks it wants. That seems like it would be more generally
useful, and would be feasible to support on multiple architectures. Though I'd
probably prefer to avoid even that, e.g. in favor of providing enough information
in other ways so that userspace can (somewhat easily) deduce how KVM will behave
for a giving mapping.
> > There is no easy way for VFIO to know to set it, and the kernel will
> > not allow switching a cachable VMA to non-cachable anyhow.
>
> > So all it does is make it harder to create a memslot.
>
> Oliver had mentioned earlier that he would still prefer a memslot flag as
> VMM should convey its intent through that flag:
>
> https://lore.kernel.org/all/aAdKCGCuwlUeUXKY@linux.dev/
> Oliver, could you please confirm if you are convinced with not having this
> flag? Can we rely on MT_NORMAL in vma mapping to convey this?
Is MT_NORMAL visable and/or controllable by userspace?
next prev parent reply other threads:[~2025-06-06 17:57 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-24 1:39 [PATCH v6 0/5] KVM: arm64: Map GPU device memory as cacheable ankita
2025-05-24 1:39 ` [PATCH v6 1/5] KVM: arm64: Block cacheable PFNMAP mapping ankita
2025-05-26 15:25 ` Jason Gunthorpe
2025-05-27 4:04 ` Ankit Agrawal
2025-06-06 18:11 ` Sean Christopherson
2025-06-09 12:24 ` Jason Gunthorpe
2025-06-09 14:21 ` Sean Christopherson
2025-05-24 1:39 ` [PATCH v6 2/5] KVM: arm64: New function to determine hardware cache management support ankita
2025-05-27 0:25 ` Jason Gunthorpe
2025-05-24 1:39 ` [PATCH v6 3/5] kvm: arm64: New memslot flag to indicate cacheable mapping ankita
2025-05-27 0:26 ` Jason Gunthorpe
2025-05-27 4:33 ` Ankit Agrawal
2025-06-02 4:42 ` Ankit Agrawal
2025-06-06 17:57 ` Sean Christopherson [this message]
2025-06-13 19:38 ` Oliver Upton
2025-06-16 11:37 ` Ankit Agrawal
2025-05-24 1:39 ` [PATCH v6 4/5] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags ankita
2025-06-06 18:14 ` Sean Christopherson
2025-05-24 1:39 ` [PATCH v6 5/5] KVM: arm64: Expose new KVM cap for cacheable PFNMAP ankita
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