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s=arc-20220608; d=hostedemail.com; t=1746794866; a=rsa-sha256; cv=none; b=JzdxtyEQlhe65nonmvzDpfCRcsHO49r5mOW37tQqA5jSED6zYVN7CUx618yArLhm0HrU/q s3sODMaQCIss+qTpv20+CzwbJkVXmG+oh3dYsbpRiKLWJ2bv/mTijGLJMLH7ag5NledzMr sNiDfcZ3qvarB5+qTcABbQnfS/BrwlI= ARC-Authentication-Results: i=1; imf29.hostedemail.com; dkim=none; dmarc=fail reason="SPF not aligned (relaxed), No valid DKIM" header.from=arm.com (policy=none); spf=pass (imf29.hostedemail.com: domain of cmarinas@kernel.org designates 147.75.193.91 as permitted sender) smtp.mailfrom=cmarinas@kernel.org Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 9694FA41865; Fri, 9 May 2025 12:47:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D4DBC4CEEF; Fri, 9 May 2025 12:47:38 +0000 (UTC) Date: Fri, 9 May 2025 13:47:36 +0100 From: Catalin Marinas To: Ankit Agrawal Cc: Jason Gunthorpe , Oliver Upton , Sean Christopherson , Marc Zyngier , "joey.gouly@arm.com" , "suzuki.poulose@arm.com" , "yuzenghui@huawei.com" , "will@kernel.org" , "ryan.roberts@arm.com" , "shahuang@redhat.com" , "lpieralisi@kernel.org" , "david@redhat.com" , Aniket Agashe , Neo Jia , Kirti Wankhede , "Tarun Gupta (SW-GPU)" , Vikram Sethi , Andy Currid , Alistair Popple , John Hubbard , Dan Williams , Zhi Wang , Matt Ochs , Uday Dhoke , Dheeraj Nigam , Krishnakant Jaju , "alex.williamson@redhat.com" , "sebastianene@google.com" , "coltonlewis@google.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "ardb@kernel.org" , "akpm@linux-foundation.org" , "gshan@redhat.com" , "linux-mm@kvack.org" , "ddutile@redhat.com" , "tabba@google.com" , "qperret@google.com" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags Message-ID: References: <20250423130323.GE1648741@nvidia.com> <20250429141437.GC2260709@nvidia.com> <20250429164430.GD2260709@nvidia.com> <20250429181926.GE2260709@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 69DBE120008 X-Rspam-User: X-Stat-Signature: wxggwqomoeah5ypa6mpam3kngmn3g9m9 X-HE-Tag: 1746794866-981801 X-HE-Meta: U2FsdGVkX186MKLYDZQPH7S/22ZVIdtLVUGuA79E5g8OM0VObdmVoS0vRKqWgwY+xCb7kf1AqB3XQMdfEhSdUbiqsqZ8y1ntwEloXf/1RZIT7nf44hXx5fnknFzl2peluk553cRpGZcnJBEn7G0179HP1i8vWqzNVmlQwkdyX8yaYeQCOC+GCrD+PmjpIolOrZnYLLCDPNji+QoHotcvCQJxiDdL9MAyQ+J1tN/EcAeljvrg4UxYBJnvzfrJVvE1BQVRf5cn2K0tNbWSbwWg2hQf4QxR8tDPSbRo5DYoLGzz50Vs8xdMgqtQecxuV2buJ71E9cTAKJF5rCQ9zkQutRye0gyJM8PvpsjXuyjhN2vg0tLyJLWf/GsNRvEgB/rrzZvYJxNeS2vMypAKhrxHDXaSF+UGPq2lQ1TpbGtEgZ73iWuGSgaBjIzS8FG51LRsybi31E7uHUK47Qb7x7RDEs2DENa4+1tSSPn74HBvDAJT0QdPc6fwvZ6cL38K98tak8N2ban+tRegWJt/dyUW/IZ1y+QfMVGxVFb2fbGQa21m0vRHLvJsxx0ip9yAVvCGZ/sY5HXQaWsmMy4A9ofM8gynGEhlsKyf3Waj5bLqfXdAI7oS0apigkVQoW5mx3IVMmYqYI284JmDa9a4fDRmUCbFYviZAFIGPBSUFC7Y3d0C8n9xS6I+ssY2vyoS1efT9tUBlA9caBNpUR33LAq6yeXaRDr/C08TY2MMTVzEvtsAu90UQNmP7VegYBUMGPIxsm4fAvGofviKQg6bY9vh7yoTRHlUZ2LiDwTx2idtc3lDIwj0ZlE4Tl5kAnszPdPtH0RxN4NZ9a54I5KdtdYPqESY1HvCcLJA1PasHzH8edc429r80qoWWTIfGgGtxee+IuKnvjJsM8jTvrVZr9zw6GB9fcOcBddTtVwiXfh1CA0+fnsG3SSr/jM1AyEUGaXgkFzHnVzysLfWJhdX4S0 rI/Gp01n MTtDo0Bs629PJF30XGUFnAgD/IOGKOoZPGPyhFDzREtYfrwDsTOdHVmh1GYXCDd68T3CCspWQpihlZr1emSjCAaIZj/jToQS7SRj6akhLJe5lcr3NsW8Tli9SbqS3tHN3LF8l9tU3vBqeU1tXT2BU+XVsOanK8YH0Gfbb11RVztB1QHYUNZAl0nMbmmkGljOVACiaxb+Ai69d8CetgoUuED/xChqOuviFHN9Wl/AGniN+OGdp74eS3SpKqp4YPg12MKYhRGc2zEOtLCC296IHSAtj+RHNRNyUB+DNo2d1QrfuL6jtB+9vsZUS1V8SCueBIKmusR9876uuaNbUiB+pZhrzLLe1bw8D96jyX/XeG5rq9YhcctPqH6VRTi9FhftUS1T17k4xDOZiD3g= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Wed, May 07, 2025 at 03:26:05PM +0000, Ankit Agrawal wrote: > >> Unless FWB implies CTR_EL0.DIC (AFAIK, it doesn't) we may be > >> restricting some CPUs. > > > > Yes, it will further narrow the CPUs down. > > > > However, we just did this discussion for BBML2 + SMMUv3 SVA. I think > > the same argument holds. If someone is crazy enough to build a CPU > > with CXLish support and uses an old core without DIC, IDC and S2FWB > > then they are going to have a bunch of work to fix the SW to support > > it. Right now we know of no system that exists like this.. > > > > Jason > > Catalin, do you agree if I can go ahead and add the check for > ARM64_HAS_CACHE_DIC? As long as we don't leave out some hardware that has FWB but not DIC, that's fine by me. -- Catalin