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From: Jane Chu <jane.chu@oracle.com>
To: Dan Williams <dan.j.williams@intel.com>,
	vishal.l.verma@intel.com, nvdimm@lists.linux.dev
Cc: Linux-MM <linux-mm@kvack.org>, Joao Martins <joao.m.martins@oracle.com>
Subject: Re: Barlopass nvdimm as MemoryMode question
Date: Thu, 7 Mar 2024 16:30:42 -0800	[thread overview]
Message-ID: <a0f62478-94d5-4629-8a81-81d6876beaec@oracle.com> (raw)
In-Reply-To: <65ea2c1a441d_12713294d9@dwillia2-mobl3.amr.corp.intel.com.notmuch>

Add Joao.

On 3/7/2024 1:05 PM, Dan Williams wrote:

> Jane Chu wrote:
>> Hi, Dan and Vishal,
>>
>> What kind of NUMAness is visible to the kernel w.r.t. SysRAM region
>> backed by Barlopass nvdimms configured in MemoryMode by impctl ?
> As always, the NUMA description, is a property of the platform not the
> media type / DIMM. The ACPI HMAT desrcibes the details of a
> memory-side-caches. See "5.2.27.2 Memory Side Cache Overview" in ACPI
> 6.4.

Thanks!  So, compare to dax_kmem which assign a numa node to a newly 
converted pmem/SysRAM region,  w.r.t. pmem in MemoryMode, is there any 
clue that kernel exposes(or could expose) to userland about the extra 
latency such that userland may treat these memory regions differently?

thanks,

-jane



  reply	other threads:[~2024-03-08  0:30 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-07 20:33 Jane Chu
2024-03-07 21:05 ` Dan Williams
2024-03-08  0:30   ` Jane Chu [this message]
2024-03-08  0:49     ` Dan Williams
2024-03-08  1:42       ` Jane Chu
2024-03-08  1:57         ` Jane Chu
2024-03-08  2:53           ` Dan Williams

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