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Sun, 12 May 2024 13:07:43 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id KTRoMR+/QGazUAAAD6G6ig (envelope-from ); Sun, 12 May 2024 13:07:43 +0000 Date: Sun, 12 May 2024 15:07:42 +0200 From: Michal Hocko To: Adam Manzanares , Davidlohr Bueso Cc: "lsf-pc@lists.linux-foundation.org" , "dan.j.williams@intel.com" , "jonathan.cameron@huawei.com" , "dave@stgolabs.net" , Fan Ni , "dave.jiang@intel.com" , "ira.weiny@intel.com" , "alison.schofield@intel.com" , "vishal.l.verma@intel.com" , "gourry.memverge@gmail.com" , "wj28.lee@gmail.com" , "rientjes@google.com" , "ruansy.fnst@fujitsu.com" , "shradha.t@samsung.com" , "mcgrof@kernel.org" , Jim Harris , "linux-mm@kvack.org" , "linux-cxl@vger.kernel.org" , "linux-pci@vger.kernel.org" Subject: Re: [LSF/MM/BPF TOPIC] CXL Development Discussions Message-ID: References: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspamd-Queue-Id: 411A514002C X-Stat-Signature: 1hdmghubek9ojxokycseu6hrwwe1nr6q X-Rspam-User: X-Rspamd-Server: rspam11 X-HE-Tag: 1715519266-142164 X-HE-Meta: U2FsdGVkX19Pu3SCJEw7w4ABQZ2jtVUCQk4vn1Cx5jjZvDcM3sKv5GdzxRB87D4vlqPqzKM2g02QUN6gsv3tlPIMEoZ4aGR94yhu9rBMm66Pom/rre9oSQ2H8kijFHekdz8eWAdUgpX5Z+8oDclvdP5sgi9dYmSzn7uMSp62rISxWNumrIPEY1UQm6iu2D6IdrUKDkZfxLe5TTSz/5wOKN9bznp9JLwXBrQ6/vjBJQkFAn9hW+GjBY7GV9dPKbhw1uEIZFmG7i0Wr2X6HmxlyDbDwoEBktmhertS+QMBdW0/FbMkhAYRD27z+Tbl+jEjBe3/i6xXxhAZHSfXE/9zVCZ1mYFRDLCLaKm07DZDsWzw2nBaYqDUrtcqinRNiArvpxlUadNPHGNWbfVIFKzJjlGHfFkNsfryuvfj7KynxrNSmEoyrZR/8cczuLvTjNN9SoQTHsYyUXM99jMn8B/S+r2/dZ5nBAR45X7t2I2blfSpr/eH8B8LRQG9cHSodtxG4+OqAiYY7pS/HyEcsY2axwAKIIs68bvbzXpxGOcKjmMPX6iDbT8Si40KZ1qGWd6aKEhZw7vnLjjf3XwTP4yL3uPGoELrs/zIkZYAuS2vXE8F4wFaImqG4DlKfL2eoXue4Hf7QmvcFpFbYAeskDlwsz3dunCXkNDTDdUSLcpOJB4GZD83qtCA76gNPArXkYEdXSgp+PRkIHl6WEyPHug6P58mGsTA7HF8Hswzi+4Adv5OHYSgijABDGYZu52ZjRggmKeVkkQELpiHCXiSB+FbaxasLncBfefEzcIDaTAg7uzdiduT3Bv4joPV/9ddWcJfv7aOrzVL/m5/FFTJuH7Nq7DnlI2pLHMohzb6j18mzRboGTzYSyjINWoDqLWVZR6+5pMYdUnTqaHnMps8Bca3/XqRiDs5PiPFU6sbU5vYUxlDMAjOVn5N9Mwmr6STvN8RP1BjmJl5TTXNmszFoho uc/nulCB 4MqKUivj6goXrc0SCZbW/nYbbhNXWSX0D0GTmwT3b/nwKXdvm4prtn3N5Kurj62xLNIu2NwkYRzlQXJZcKkjw64ensee5vueVpRnB0XBV6uXUDA2/kZNQame0evkMHGl0gJZpOA0Kc/byXAi5M/B1mOEnBJEe0ITlWqbc9peEKMz05LnE9EZpQETAB4fGsY/+hzf3lIcKpQfa6RrQCD3N02MHTxZJw38LKhGK+YFf2bRTGgov8X722L6q45MZdcrQx6dMvz/RSnqpCTOJMnP4lCpbUk3zg+q3VpEUpGIz451jxr5DG2S9OTiscmabyOcLIF8+oEgbIyOLVGg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: [add Davidlohr] On Wed 08-05-24 18:35:50, Adam Manzanares wrote: > On Tue, May 07, 2024 at 01:48:46PM +0200, Michal Hocko wrote: > > On Mon 06-05-24 19:27:10, Adam Manzanares wrote: > > > Hello all, > > > > > > I would like to have a discussion with the CXL development community about > > > current outstanding issues and also invite developers interested in RAS and > > > memory tiering to participate. > > > > > > The first topic I believe we should discuss is how we can ensure as a group > > > that we are prioritizing upstream work. On a recent upstream CXL development > > > discussion call there was a call to review more work. I apologize for not > > > grabbing the link, but I believe Dave Jiang is leveraging patchwork and this > > > link should be shared with others so we can help get more reviews where needed. > > > > > > The second topic I would like to discuss is how we integrate RAS features that > > > have similar equivalents in the kernel. A CXL device can provide info about > > > memory media errors in a similar fashion to memory controllers that have EDAC > > > support. Discussions have been put on the list and I would like to hear thoughts > > > from the community about where this should go [1]. On the same topic CXL has > > > port level RAS features and the PCIe DW series touched on this issue [2] > > > > > > The third topic I would like to discuss is how we can get a set of common > > > benchmarks for memory tiering evaluations. Our team has done some initial > > > work in this space, but we want to hear more from end users about their > > > workloads of concern. There was a proposal related to this topic, but from what > > > I understand no meeting has been held [3]. > > > > > > The last topic that I believe is worth discussion is how do we come up with > > > a baseline for testing. I am aware of 3 efforts that could be used cxl_test, > > > qemu, and uunit testing framework [4]. > > > > This seems to be quite a lot for a single time slot. I think it would > > make sense to split that into more slots. WDYT? > > +1. I think the performance implications of CXL memory and how it relates > to existing memory management code tackling performance differentiated memory > would be nice to separate. I think Davidlohr would be a great candidate to > lead this discussion. WDYT Davidlohr? -- Michal Hocko SUSE Labs