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Tue, 7 May 2024 11:48:47 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id xDo2Bx8VOmYdBAAAD6G6ig (envelope-from ); Tue, 07 May 2024 11:48:47 +0000 Date: Tue, 7 May 2024 13:48:46 +0200 From: Michal Hocko To: Adam Manzanares Cc: "lsf-pc@lists.linux-foundation.org" , "dan.j.williams@intel.com" , "jonathan.cameron@huawei.com" , "dave@stgolabs.net" , Fan Ni , "dave.jiang@intel.com" , "ira.weiny@intel.com" , "alison.schofield@intel.com" , "vishal.l.verma@intel.com" , "gourry.memverge@gmail.com" , "wj28.lee@gmail.com" , "rientjes@google.com" , "ruansy.fnst@fujitsu.com" , "shradha.t@samsung.com" , "mcgrof@kernel.org" , Jim Harris , "linux-mm@kvack.org" , "linux-cxl@vger.kernel.org" , "linux-pci@vger.kernel.org" Subject: Re: [LSF/MM/BPF TOPIC] CXL Development Discussions Message-ID: References: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> X-Rspam-User: X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 15A1314001F X-Stat-Signature: hmstj4gts1se1jeue73eh9ni9y7oog5f X-HE-Tag: 1715082528-972410 X-HE-Meta: U2FsdGVkX18MHPQKL3EgRUuQsFUzHGIBPnaAbmcuRUlv2vf5eJL71l0o/U+/52Jaqnu2gxDsDYFfvot5hkaJpMw1AHzZ9l5HKBPauM9bVO2FnrdRv/xol6VMc3EpJZ5e83UMinw1bhQMJfS0qh+MCnwkCAwDOYNkw5b9F/6hXYu0hJqF9QBmBJOPveUT6FxD6gi2u+A7vbmcUl885WCSjknRbDHNQgf+rOVwI+4sK2MiOTNzMLiez0IYmSPTIKsmHPBARX0+LW2iNrOOG/Vysqe0LlgCh3zntLpyOQdG9MItIDXUH+kI9P5G4RsKVGOE12PJ43MkA1L/coCrAXVQvSH7HBRhEJE7my9S5bzQwMdhow4iUgYubff9fBOUkTaVCk8b/arho9U8dCTexTsT6isitt7rg5dvDkO+iDgn63EtJ5Jmz/qMf7xqXte/x4uPUhAPenEC2F2mQpcPcCv4EJKAk/nUnnZE6MWLcBgahNtV6/vX3G4oRCQ1AARL9ujl1aWWPOLm2dtvw7Y/EYRXTjG8PWckUZo2Z0aTd+Gzp25xQ0ysb+LHm+GDYAdluiF4Xcf9i/gSGdyPYQHqVVTT+RCmvjV/Ef7V1ZFWX3x+iFqRzRGKRpdw0vx9Cxdbzi7Lw5PYZ4wyuNJxt8VoavJ5v2m32FmcoX0G/QKxuztNeHXz0L3xz3vRK+WhHCBLHvlRtCWnxb7SSh2n6xVZhqsFB/a3fhYCKyvEVQCevtwjW/om36DGLq8ynCNAIs1d6aEVPLSB9epsTkWcvnBQL52oRgGQR+7pA0AC6Itcs4zXcjdSO+9qBZ0/Ngx7djLM4Wgo5TVfEkHBzNagDXqRhSQ0LsnjRblYdUe2dDVX37o/kt7Tzn/YPOhPWnXbnHvmFAMbF6KXruOI46XvdEPoK8lfEBudpBJ2wJJ1mr0EZEBmKj8cfjBQ2yCK3tnAJKk/kNc2E4w4g1HdIeOtLILyGy0 wJVF2YiZ 6Vvwpyfz7ssMLAaYt0HqKNUPH1B19Dv+in4H4zf8OxA6z5NxqqZDZAtYkIMfZqoloW3U5y0x/Oj4ebftWKiv6iOHI+1qDaX2CJEz6iYkH1GDqK1lu7LH7sjrbVjq6KPbsrhWrj+Nd42GzU1IRkQuXnth/AaOeDQVcXebo88YZenyQoil14iB3NfFX8MWrOC7xHajDpJ2+pugszzXVWFg9KZOcbT2vQEE1ESKMdioQigLs9vEgmVEKMc+a9BD+0RzjFjmr8l7amLHw2Y1lTIxb/8tBCpSi6cEyNOOsID+AgstpCgS4WABqdxX7scNyD3OvrVLGw2moLj4ssoI= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon 06-05-24 19:27:10, Adam Manzanares wrote: > Hello all, > > I would like to have a discussion with the CXL development community about > current outstanding issues and also invite developers interested in RAS and > memory tiering to participate. > > The first topic I believe we should discuss is how we can ensure as a group > that we are prioritizing upstream work. On a recent upstream CXL development > discussion call there was a call to review more work. I apologize for not > grabbing the link, but I believe Dave Jiang is leveraging patchwork and this > link should be shared with others so we can help get more reviews where needed. > > The second topic I would like to discuss is how we integrate RAS features that > have similar equivalents in the kernel. A CXL device can provide info about > memory media errors in a similar fashion to memory controllers that have EDAC > support. Discussions have been put on the list and I would like to hear thoughts > from the community about where this should go [1]. On the same topic CXL has > port level RAS features and the PCIe DW series touched on this issue [2] > > The third topic I would like to discuss is how we can get a set of common > benchmarks for memory tiering evaluations. Our team has done some initial > work in this space, but we want to hear more from end users about their > workloads of concern. There was a proposal related to this topic, but from what > I understand no meeting has been held [3]. > > The last topic that I believe is worth discussion is how do we come up with > a baseline for testing. I am aware of 3 efforts that could be used cxl_test, > qemu, and uunit testing framework [4]. This seems to be quite a lot for a single time slot. I think it would make sense to split that into more slots. WDYT? -- Michal Hocko SUSE Labs