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Thu, 25 Jan 2024 09:09:19 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id w128-20020a626286000000b006dde0724247sm180477pfb.149.2024.01.25.09.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 09:09:19 -0800 (PST) Date: Thu, 25 Jan 2024 09:09:14 -0800 From: Deepak Gupta To: Stefan O'Rear Cc: rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, "kito.cheng@sifive.com" , Kees Cook , Andrew Jones , paul.walmsley@sifive.com, Palmer Dabbelt , Conor Dooley , cleger@rivosinc.com, Atish Patra , Alexandre Ghiti , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Alexandre Ghiti , Jonathan Corbet , Albert Ou , oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, "Eric W. Biederman" , shuah@kernel.org, Christian Brauner , guoren , samitolvanen@google.com, Evan Green , xiao.w.wang@intel.com, Anup Patel , mchitale@ventanamicro.com, waylingii@gmail.com, greentime.hu@sifive.com, Heiko Stuebner , Jisheng Zhang , shikemeng@huaweicloud.com, david@redhat.com, Charlie Jenkins , panqinglin2020@iscas.ac.cn, willy@infradead.org, Vincent Chen , Andy Chiu , Greg Ungerer , jeeheng.sia@starfivetech.com, mason.huo@starfivetech.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bhe@redhat.com, ruscur@russell.cc, bgray@linux.ibm.com, alx@kernel.org, baruch@tkos.co.il, zhangqing@loongson.cn, Catalin Marinas , revest@chromium.org, josh@joshtriplett.org, joey.gouly@arm.com, shr@devkernel.io, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [RFC PATCH v1 02/28] riscv: envcfg save and restore on trap entry/exit Message-ID: References: <20240125062739.1339782-1-debug@rivosinc.com> <20240125062739.1339782-3-debug@rivosinc.com> <23d023c0-27cf-44fa-be0a-000d1534ef86@app.fastmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <23d023c0-27cf-44fa-be0a-000d1534ef86@app.fastmail.com> X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 21DCE40024 X-Stat-Signature: 8ogkf3hk86bz8ei19xh4jnpsh5dzqj3o X-HE-Tag: 1706202560-690741 X-HE-Meta: U2FsdGVkX18pNacOYOgVtVjeb89j+IhxOCYvL9kwMi2k+gPlLmuttIcMrnNc5C2ki9v0l2Rf6z/ke0EWspmLM0m7ypn2Z418JCdLoWsCs45zUTj/kGueWEskBblG8Z/L5Nw20Snj3ipYi5PBQUY38DuUE8OK4gaYJtbWF9maCPJW/OdWpuL5OZk5Q3UfoADI5t+v2i4OupCb45QZQKgtGqKBDP2iGIowQt0+lSmGmYU2UblxQ5VT8mCwfk2TH+qbFtHk2a64cznArjtL2MXpfMfvetfckr0SyeYrboSOXh7/HqSFccS8ltVlbOtXCzGFeX7yf0Mb7WafKRdoaVJv1QcAYNWZlQldtR5n9LNHnDtUNpleJWT2K1qriEL6vEiZvahb5KnTbdQcHpvnrnu1yrgZoBcKqJCxYyE1Ax74byz2itorA0CD8iFIcSVkgk4NgMZA3D/fPCig6wm5OHpSKY4ip8D7GJIW59JP8mKMk/DOKK5Dch8U/g7ZhtgumK2b/wuneZ/T91jRJ8eK5uo0WS+c7ffdEsb+dHPsDm09kz1280bFzTOVBOWGeWwghQgzb/P0rIfbTnlLHv8lRD2+RQUPAwl51sQOcyHR54ijYjNnjkMSVli2GwM7022kP7wL6yRdgJ71i+qxpExYUJFZ1wdKRjX2zjnDtwzuDxVDPPmAM5uqm/lOnOOZisNp4r5z2puHcaQP7V7crKT/ZWNI9ULqqH6Ms655t3JRIG3s14N11+hmmasMLevpXcY22cdQUwspK2bkGcIN06H5dRt4QAFhZvMCYBY5T2p9ifwIjd/Eb10ySU838K+mGDS22pJpjmoYhD9P5Ua165DZ9sOIlt0Xgkgv0lLUXywl8GUPtB33+1/m1gNDCRYfNcreAbLGth7g7bMsAnSAqOBE2ipA2e9qTmbdsI+ltgSyScbgDlKjAfxvGtExZA+o2CpEUrozUObldGh2eFWrjnivkoE Za3ujWOr t4TfDQm9GMGrHq5VyCv3qk6ZQEj2UsLrFnvKDe5Mn4d0mOuGvLmYu8zSwUhg81N0gQ4HKXev1F3WIxYilJZxStWSnOSWAe3F2uSV6y/N1Q0MvQiqOVNmnGfGTvM9RIXwOFdPdntWjnYLsovIAgQ+v5xhCMFumA+jwFD9lMXFzOnmk70ANrCwzK+TRAZofJgp1QHIS25WIGpqSGBKnQONNQ/RJY2h1Bz5UJ8PZzFjQoWpDeQ4dEthV+kj0hefXIyfK4aN8LGrtNeU1jEb7y5/VytLsnFM1RzQ3mNnBYLFJGUOSG/nHyi2SAXnbgdtqPtH0YZ/a/4Mc0qssgep5TNemlEn/ttbkIemHBl2q/w8K8xMbuGLeju31FS81qvJi/VvWkLA2lc2RigUUfdJvafd501FUMq8Jimc8wrqQI1/dz36Rx72Q+CYLR5elT5SVi6uNTyBjdXJsBkoOWnSvxngIxjOaNOaXeWallcmjrty81HCGujOGiY0KExHMs8elQ2sRWjuldN3PNg4OQvfxzW81wKF+g0w4AkkeWo2LvwrxmrG7XX2Ho5T55rnRow== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Thu, Jan 25, 2024 at 02:19:29AM -0500, Stefan O'Rear wrote: >On Thu, Jan 25, 2024, at 1:21 AM, debug@rivosinc.com wrote: >> From: Deepak Gupta >> >> envcfg CSR defines enabling bits for cache management instructions and soon >> will control enabling for control flow integrity and pointer masking features. >> >> Control flow integrity enabling for forward cfi and backward cfi is controlled >> via envcfg and thus need to be enabled on per thread basis. >> >> This patch creates a place holder for envcfg CSR in `thread_info` and adds >> logic to save and restore on trap entry and exits. > >Should only be "restore"? I don't see saving. It's always saved in `thread_info` and user mode can't change it. So no point saving it. > >> >> Signed-off-by: Deepak Gupta >> --- >> arch/riscv/include/asm/thread_info.h | 1 + >> arch/riscv/kernel/asm-offsets.c | 1 + >> arch/riscv/kernel/entry.S | 4 ++++ >> 3 files changed, 6 insertions(+) >> >> diff --git a/arch/riscv/include/asm/thread_info.h >> b/arch/riscv/include/asm/thread_info.h >> index 574779900bfb..320bc899a63b 100644 >> --- a/arch/riscv/include/asm/thread_info.h >> +++ b/arch/riscv/include/asm/thread_info.h >> @@ -57,6 +57,7 @@ struct thread_info { >> long user_sp; /* User stack pointer */ >> int cpu; >> unsigned long syscall_work; /* SYSCALL_WORK_ flags */ >> + unsigned long envcfg; >> #ifdef CONFIG_SHADOW_CALL_STACK >> void *scs_base; >> void *scs_sp; >> diff --git a/arch/riscv/kernel/asm-offsets.c >> b/arch/riscv/kernel/asm-offsets.c >> index a03129f40c46..cdd8f095c30c 100644 >> --- a/arch/riscv/kernel/asm-offsets.c >> +++ b/arch/riscv/kernel/asm-offsets.c >> @@ -39,6 +39,7 @@ void asm_offsets(void) >> OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); >> OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); >> OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); >> + OFFSET(TASK_TI_ENVCFG, task_struct, thread_info.envcfg); >> #ifdef CONFIG_SHADOW_CALL_STACK >> OFFSET(TASK_TI_SCS_SP, task_struct, thread_info.scs_sp); >> #endif >> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S >> index 54ca4564a926..63c3855ba80d 100644 >> --- a/arch/riscv/kernel/entry.S >> +++ b/arch/riscv/kernel/entry.S >> @@ -129,6 +129,10 @@ SYM_CODE_START_NOALIGN(ret_from_exception) >> addi s0, sp, PT_SIZE_ON_STACK >> REG_S s0, TASK_TI_KERNEL_SP(tp) >> >> + /* restore envcfg bits for current thread */ >> + REG_L s0, TASK_TI_ENVCFG(tp) >> + csrw CSR_ENVCFG, s0 >> + > >This is redundant if we're repeatedly processing interrupts or exceptions >within a single task. We should only be writing envcfg when switching >between tasks or as part of the prctl. > >We need to use an ALTERNATIVE for this since the oldest supported hardware >does not have envcfg csrs. Yeah fixing that in next series. Thanks > >-s > >> /* Save the kernel shadow call stack pointer */ >> scs_save_current >> >> -- >> 2.43.0 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv