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Wed, 09 Apr 2025 07:43:46 -0700 (PDT) Date: Wed, 9 Apr 2025 07:43:42 -0700 From: Deepak Gupta To: Alexandre Ghiti Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Zong Li Subject: Re: [PATCH v12 03/28] riscv: zicfiss / zicfilp enumeration Message-ID: References: <20250314-v5_user_cfi_series-v12-0-e51202b53138@rivosinc.com> <20250314-v5_user_cfi_series-v12-3-e51202b53138@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 1050B180010 X-Stat-Signature: qp7hub57hophbetrjawzohgdy1dgnuga X-Rspam-User: X-HE-Tag: 1744209827-262025 X-HE-Meta: U2FsdGVkX1+Ouv1mz7aauhW1c09ZnPSl45VJsWmBl/WdSaO/lRYWRGTL3ijP7Y2MbaKy/0K54WCsd2Eu/BZLZeuLnD41oiDMzux82grsSmsZL4W2+oZIMd1/Sagx+nmGMgwSqaB74xcaLa3PWF/UCfNtwrPlLOSHMnQytinCvtzTIXQnzKSx+aupnzd5cxyH66nLBT7bNQyU/9qF6Yw3cTdtrsugOzuyyDbcELL0xyPLIRlhkLj9MFyTil+UzvtvVtfLA48sak+frqtzjAHJc6Y/Z31h8zw7UwlvTVAj8fB3BM/vN3js25vhIFd/P9OeSpSHuyJEuutqHTTrFrX3fp5nfSg5rP+w8cuIkc/buStHcUO7yEIw7Di3fP8nX4ymSGS/1k+NAJTafqTygfIQEBSYWnRRApA/QHAUassfSf6EVZC+jt3ajkl/bo2zTXkVxJpl3xUDf6rwtlQf4sHnXDEqRYLrRaVpKUByPiB2Yy3SOhjRgKVgQIE46eq8EKECJHTwF2g8AEqf3Ym71m/kJhQYx5ZvD6UAXhFxkfI60uKoOMwg1f9krMHV/IDHnim27Fk0xvY+jxqUN6gbs/ircZzGrkMeVSXs7RW05PNX8g81YwtAFb/JShqSgwybyxdnwGm3DFGnvRntl1EyaucvwvOURmNCQ6ncM0sSSYWJaaYO+IcKTTEIW4TnuhSy3L/gbKVkf1spoqvf8Rx1KoIVNvi0VywAIlf20KTodcN0MVS1jxasRTslI6PL57pyIBfspitYUsXaTHrHI7YhOjADOMIfvTm3ap19rgEyTTUX1TctWY+zSPs7SWZowKeaOjGSNF5DYB6xxMED9wKPb15cZDG/7zfMBcUtYkCZZ/3qbE+7HKelNkQNxcoivf8FMtLuHFKNRH0aP+3tRTkyE2XefqpP2yUxqIvCNe+A76vs9jxaWEh2r+S8n2oe/nxBtAxkSwQrHl8qzeq2jieE088 fRE6OTPB D49ZtHcy3rpCzQngO1FO/BC7duBOhZj1GDWxpX9jF4Ah9XV3yatHq2DnuUsNNyo3UflVeJDw2op35Z0Ey0PT1IMny2N/KZ2wb/XOCSvlo3VhGCAhL/iCRJDFjWE4FHRTHpqij48sZXNtsrX5xRBrUkzfPq2QC3v/ETC7PoraDcVp7kl2bK2VToK4fDJ6kjtmtjzBEP9r+BFsOnEmaXw4Jv3ef4FVtEO2555zXU/jCeM+e19VXHDPEWUkwKwLcI+3de2XNCGXNg83nV0d+/4GZGJdmRaec+3mYurR6RFee1nxNI/55qMlh+dnuSc6vYU5lPnZzbE7jyLMkHpWFETguecizTH+8Hds/4kYdqaCflNmpeaHYqNFclPqizohPe7ue/JHx5Lj7+RDA9x5v/FViKeWqybzoRSywWHHWuhOXZoEa5/IwjW/OokJjyfp+ElsKT9EGZKSkHC/nyxXvXqJzn80sY49e6F2EcRj+tYBQt+jVRTYkWpc7iNXMRbURJ4j5ACtODWDeCTJEQ+Re4DlnE4T2bq+tsWZg8NHscpWt0DMSmLZ8JK6gxSG1jg== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon, Apr 07, 2025 at 05:48:27PM +0200, Alexandre Ghiti wrote: > >On 14/03/2025 22:39, Deepak Gupta wrote: >>This patch adds support for detecting zicfiss and zicfilp. zicfiss and >>zicfilp stands for unprivleged integer spec extension for shadow stack >>and branch tracking on indirect branches, respectively. >> >>This patch looks for zicfiss and zicfilp in device tree and accordinlgy >>lights up bit in cpu feature bitmap. Furthermore this patch adds detection >>utility functions to return whether shadow stack or landing pads are >>supported by cpu. >> >>Reviewed-by: Zong Li >>Signed-off-by: Deepak Gupta >>--- >> arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ >> arch/riscv/include/asm/hwcap.h | 2 ++ >> arch/riscv/include/asm/processor.h | 1 + >> arch/riscv/kernel/cpufeature.c | 13 +++++++++++++ >> 4 files changed, 29 insertions(+) >> >>diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >>index 569140d6e639..69007b8100ca 100644 >>--- a/arch/riscv/include/asm/cpufeature.h >>+++ b/arch/riscv/include/asm/cpufeature.h >>@@ -12,6 +12,7 @@ >> #include >> #include >> #include >>+#include >> #include >> #include >>@@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi >> return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); >> } >>+static inline bool cpu_supports_shadow_stack(void) >>+{ >>+ return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && >>+ riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); > > >I would use riscv_has_extension_unlikely() instead of the cpu specific >variant, that would remove the need for #include . Unless >you have a good reason to do that? No I dont remember the reason. I'll fix it. When I am fixing it, and happpen to remember the reason. I'll post it. > > >>+} >>+ >>+static inline bool cpu_supports_indirect_br_lp_instr(void) >>+{ >>+ return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && >>+ riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); >>+} >>+ >> #endif >>diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>index 869da082252a..2dc4232bdb3e 100644 >>--- a/arch/riscv/include/asm/hwcap.h >>+++ b/arch/riscv/include/asm/hwcap.h >>@@ -100,6 +100,8 @@ >> #define RISCV_ISA_EXT_ZICCRSE 91 >> #define RISCV_ISA_EXT_SVADE 92 >> #define RISCV_ISA_EXT_SVADU 93 >>+#define RISCV_ISA_EXT_ZICFILP 94 >>+#define RISCV_ISA_EXT_ZICFISS 95 >> #define RISCV_ISA_EXT_XLINUXENVCFG 127 >>diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h >>index 5f56eb9d114a..e3aba3336e63 100644 >>--- a/arch/riscv/include/asm/processor.h >>+++ b/arch/riscv/include/asm/processor.h >>@@ -13,6 +13,7 @@ >> #include >> #include >>+#include >> #define arch_get_mmap_end(addr, len, flags) \ >> ({ \ >>diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>index c6ba750536c3..82065cc55822 100644 >>--- a/arch/riscv/kernel/cpufeature.c >>+++ b/arch/riscv/kernel/cpufeature.c >>@@ -150,6 +150,15 @@ static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, >> return 0; >> } >>+static int riscv_cfi_validate(const struct riscv_isa_ext_data *data, >>+ const unsigned long *isa_bitmap) >>+{ >>+ if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) >>+ return -EINVAL; >>+ >>+ return 0; >>+} >>+ >> static const unsigned int riscv_zk_bundled_exts[] = { >> RISCV_ISA_EXT_ZBKB, >> RISCV_ISA_EXT_ZBKC, >>@@ -333,6 +342,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >> __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, >> riscv_ext_zicboz_validate), >> __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), >>+ __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts, >>+ riscv_cfi_validate), >>+ __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts, >>+ riscv_cfi_validate), >> __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), >> __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), >> __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), >> > >With the above comment fixed, you can add: > >Reviewed-by: Alexandre Ghiti > >Thanks, > >Alex >