From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67119C369B8 for ; Tue, 15 Apr 2025 10:51:55 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 87C6C2800EC; Tue, 15 Apr 2025 06:51:52 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 8294A2800BD; Tue, 15 Apr 2025 06:51:52 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 62ECE2800EC; Tue, 15 Apr 2025 06:51:52 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id 3A2CE2800BD for ; Tue, 15 Apr 2025 06:51:52 -0400 (EDT) Received: from smtpin26.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id BCC1814069C for ; Tue, 15 Apr 2025 10:51:53 +0000 (UTC) X-FDA: 83335962906.26.D6C1D4F Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) by imf14.hostedemail.com (Postfix) with ESMTP id D1B3F100005 for ; Tue, 15 Apr 2025 10:51:51 +0000 (UTC) Authentication-Results: imf14.hostedemail.com; dkim=none; spf=pass (imf14.hostedemail.com: domain of cmarinas@kernel.org designates 172.105.4.254 as permitted sender) smtp.mailfrom=cmarinas@kernel.org; dmarc=fail reason="SPF not aligned (relaxed), No valid DKIM" header.from=arm.com (policy=none) ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1744714311; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kUWq4hbbLYmJEqMCHxgFxp0FOO2Wr6bianiqlQZahxQ=; b=7L+ksrkAIswj4q95+0oEWZhayiYaK3XMpkerR3MdM0JoIOgKUreGMDBpLh1oWOzNhvSEER X2ioH3PP9CLLh1N7MdAlOd0begZpePNCeD6L1YblCIglZvqBqJiBG+PUWooGP114DIol5o 7wtKhdGDfGhwuF85l4RycFv915X7vRo= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1744714311; a=rsa-sha256; cv=none; b=LLcYPPf+Ac7dhCS7whopxEHRmLQUbCFKyf0fBcw38SdhmyyvZs5BniUYJjDDD4ZY+c6ByW 6JcxfSNEnWz8aEQlIvd5oyNkZtVdplGlWB79ukIhIj/StY29xV1DuCzekym8ijslpRPSzK 9sJwemKJoniNL9cXSe8pIlAa9dB3f3c= ARC-Authentication-Results: i=1; imf14.hostedemail.com; dkim=none; spf=pass (imf14.hostedemail.com: domain of cmarinas@kernel.org designates 172.105.4.254 as permitted sender) smtp.mailfrom=cmarinas@kernel.org; dmarc=fail reason="SPF not aligned (relaxed), No valid DKIM" header.from=arm.com (policy=none) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 920B86112C; Tue, 15 Apr 2025 10:51:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C28DC4CEE7; Tue, 15 Apr 2025 10:51:48 +0000 (UTC) Date: Tue, 15 Apr 2025 11:51:45 +0100 From: Catalin Marinas To: Ryan Roberts Cc: Will Deacon , Pasha Tatashin , Andrew Morton , Uladzislau Rezki , Christoph Hellwig , David Hildenbrand , "Matthew Wilcox (Oracle)" , Mark Rutland , Anshuman Khandual , Alexandre Ghiti , Kevin Brodsky , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 11/11] arm64/mm: Batch barriers when updating kernel mappings Message-ID: References: <20250304150444.3788920-1-ryan.roberts@arm.com> <20250304150444.3788920-12-ryan.roberts@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Stat-Signature: 4i68wefqjnputoqqpq93qqzyo5376a1k X-Rspam-User: X-Rspamd-Queue-Id: D1B3F100005 X-Rspamd-Server: rspam08 X-HE-Tag: 1744714311-840504 X-HE-Meta: U2FsdGVkX1/m8dLF0mo66DUE2LKitgEqIUXDh/XOl3Pe+QnrUa5vbwqV1MBx5RoKKIrGE+dtJIEghDBHBqyVfjNZ1W1a579NJMImBv2UFDcTdhzX3XOOOYYtOObfC6c4uv/eTj4twBA0MbJMb0A4pAa8lMB5LOCf7ZyAj3w5GTaKdSN6QNjnFyjB+m3F4YWGl8poHqp8Qu6NmrwC5NSOuYHbmLT7exfm9uQK84VMJIKDXfgRWv6uzM09rxrC27P4p8YMkGypYX7+a0+P3W61cwhGuk7VIC5RuglnaQCJPSGbOgm/dyYnnhThoZ1ZBRYufEQnEf1H3JvNfQsQY2lsp9Z0CWXHtgVl5gTT+t6CZ2ADQzCZ4i3l8y0rQC+LOLq5QacpyHYSqPrgGFzPtybCNCj17VFD+fPiPxqgOU/R76XWRiUbJhl4VzAyxUudqzDV3BFjpFqLIh1l//68YHtZMxVc/+qSlEUfkpm4vHkcuEly9xKX2diisZZ7Xl4omPJVE0gT394e0iC4EpMmaLVNIr/55ku6xHnLOfu1Ey5toEEmDLUB7RKVCmcQwYprqcxlvJC7rLRUtc49CgRPUrENl9l8WvNs4mv1sqRXdoAX9HRFvnQAy9hSSBDBMgfiXZ57MiSK5Ymt593zGN1fVm/Ccfqae6iYEf4m6I/vQSCcRn+MZ7hw9R5ftJv3feW9X0U0FGT/ejeE3lXL7m066b4c2pSvilIASs58NZgbz4Si8OlJ6wEL8SCwEdN5l3NqKsnCgH8B2SzGpaUrQgBW242amkU/EazpDBpoIffEC55Zpglsl+Rsfjk7mQurmSCVMXkWbhoJ90ta+Zk1pbXp1mi88lR+Q0wxqvUJ1Mf8nzrnYc2lzNcFsH/II6gvw6hqiQhagTMhVJIinuoQAB7IXgY2hIS38UrJX+5rbyyEnlckTrZDBsJOl/EBrBBOQpKWyIgY81L97/Nx+wtC4ynw+64 KgOfSgyX +gxnRR4ez7slkd7ChyjXfLFFRLk3eJRZSTuaSvHaQ/ztPHl90zCKY0B4n9y593TS94eW4lkC9Qqwx7m5siieofIzjqiZrZdAcrrGIGzgvwMl7OMym/HHoXRk+4NIal8849NYh5V7A11Vn+XFHXkrpirah6zK9DWB+goy/UZHIM3IkU9foFWA7KYV8XbkSgAaBbq3vUjJ3SZIGa8MGQPG5TxhCn44iW3H/rqkxUFYGfWnvb3n+vCzMuL9VOe9xDMg3mZvpga9XiJRXd3knU3i+bWCYRFijBCBop4WqEbVF2PAOPtfovXLshV5X147lF3AwaDY0iegXRXSgFQPa4nR1nWOeipOLwGuUaG13 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon, Apr 14, 2025 at 07:28:46PM +0100, Ryan Roberts wrote: > On 14/04/2025 18:38, Catalin Marinas wrote: > > On Tue, Mar 04, 2025 at 03:04:41PM +0000, Ryan Roberts wrote: > >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > >> index 1898c3069c43..149df945c1ab 100644 > >> --- a/arch/arm64/include/asm/pgtable.h > >> +++ b/arch/arm64/include/asm/pgtable.h > >> @@ -40,6 +40,55 @@ > >> #include > >> #include > >> > >> +static inline void emit_pte_barriers(void) > >> +{ > >> + /* > >> + * These barriers are emitted under certain conditions after a pte entry > >> + * was modified (see e.g. __set_pte_complete()). The dsb makes the store > >> + * visible to the table walker. The isb ensures that any previous > >> + * speculative "invalid translation" marker that is in the CPU's > >> + * pipeline gets cleared, so that any access to that address after > >> + * setting the pte to valid won't cause a spurious fault. If the thread > >> + * gets preempted after storing to the pgtable but before emitting these > >> + * barriers, __switch_to() emits a dsb which ensure the walker gets to > >> + * see the store. There is no guarrantee of an isb being issued though. > >> + * This is safe because it will still get issued (albeit on a > >> + * potentially different CPU) when the thread starts running again, > >> + * before any access to the address. > >> + */ > >> + dsb(ishst); > >> + isb(); > >> +} > >> + > >> +static inline void queue_pte_barriers(void) > >> +{ > >> + if (test_thread_flag(TIF_LAZY_MMU)) > >> + set_thread_flag(TIF_LAZY_MMU_PENDING); > > > > As we can have lots of calls here, it might be slightly cheaper to test > > TIF_LAZY_MMU_PENDING and avoid setting it unnecessarily. > > Yes, good point. > > > I haven't checked - does the compiler generate multiple mrs from sp_el0 > > for subsequent test_thread_flag()? > > It emits a single mrs but it loads from the pointer twice. It's not that bad if only do the set_thread_flag() once. > I think v3 is the version we want? > > > void TEST_queue_pte_barriers_v1(void) > { > if (test_thread_flag(TIF_LAZY_MMU)) > set_thread_flag(TIF_LAZY_MMU_PENDING); > else > emit_pte_barriers(); > } > > void TEST_queue_pte_barriers_v2(void) > { > if (test_thread_flag(TIF_LAZY_MMU) && > !test_thread_flag(TIF_LAZY_MMU_PENDING)) > set_thread_flag(TIF_LAZY_MMU_PENDING); > else > emit_pte_barriers(); > } > > void TEST_queue_pte_barriers_v3(void) > { > unsigned long flags = read_thread_flags(); > > if ((flags & (_TIF_LAZY_MMU | _TIF_LAZY_MMU_PENDING)) == _TIF_LAZY_MMU) > set_thread_flag(TIF_LAZY_MMU_PENDING); > else > emit_pte_barriers(); > } Doesn't v3 emit barriers once _TIF_LAZY_MMU_PENDING has been set? We need something like: if (flags & _TIF_LAZY_MMU) { if (!(flags & _TIF_LAZY_MMU_PENDING)) set_thread_flag(TIF_LAZY_MMU_PENDING); } else { emit_pte_barriers(); } -- Catalin