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From: Oliver Upton To: Lorenzo Pieralisi Cc: Jason Gunthorpe , Catalin Marinas , ankita@nvidia.com, maz@kernel.org, suzuki.poulose@arm.com, yuzenghui@huawei.com, will@kernel.org, alex.williamson@redhat.com, kevin.tian@intel.com, yi.l.liu@intel.com, ardb@kernel.org, akpm@linux-foundation.org, gshan@redhat.com, linux-mm@kvack.org, aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com, targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com, apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com, mochs@nvidia.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com Subject: Re: [PATCH v3 2/2] kvm: arm64: set io memory s2 pte as normalnc for vfio pci devices Message-ID: References: <20231208164709.23101-1-ankita@nvidia.com> <20231208164709.23101-3-ankita@nvidia.com> <20231212181156.GO3014157@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT X-Rspamd-Queue-Id: A1FA5180025 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: zg1iqtmsu9qfxtuztamsyudskj4a1h1z X-HE-Tag: 1702572977-490001 X-HE-Meta: U2FsdGVkX19s+7LH5zckLc6vFreDa7Wone2SXMOIu1TOYKxLWEicAyPWiAR0ca+ddv5MlffyXNX07Ib5wdBm5e7S9qahv2HCQB8chZmJE69OtV70tQM7MxgwJ/4jFGxaPUX8kv75buVOp9RQzyq3BYOp+DFOiwhbcgHK3z+uj5/LpOUe1ZeerMZur5cfCxKRntIy5tmSOVVYHYeog9wkaBbqPFmMpD8lbRsm0X0VJYQMB0BXjLwFGFnR2jaP4aAW+nkRksWekiFbPacQzhmARoIdelxAPVAynxdRPVt/jB7q8F+MC01qFduSCd+MGuXyEhSpe0N7SQLbqUflCFhsilun1HVvjNLe5UE0J9zexha1Jc2bDX4d1iclmV6bukDp38a+64VXkILfr1oeFgwZe8bUlf+x5BCGJ2LLgUWWP7Tz2V6j/NbOEDEuP2pob9O3nk3xa87N75UAFP3cgfU1M+s+evVjOAJt6yogoSge0RIdgm21mojirgxdB1YU3HT4ucT++uGjDKw3m1up+6N+lpK4cS73AE2rkj97zAbAS/yZaPWjQtzzQP9zl7lXeKS8AhHnfYzlkHbKdjV9Kdnmdx6zeM+ZgV0qvsHiMJxP83XQ6H9s0PNEf/fXI/IU7C2Os0oK8eQ8Vkkqo93mdM9TVzuum60nStkEvOK+eFCNKiipW7X8YHPI/C9xY4WJmOXJSnNnEzllPH3LDqjGfHmNdmo5F0o73o7BVLLHV7bJPA4rA9b/akMmnde75IYy8EPaHrghjasvIMzsj3EOylRjXze42CZQQ1GJoQnSlXX27kXyyFC+U3HKyp3xrbAPjexr+IO8nTZ0aTkyI8j1C6EZkzSx8/lt6PMKwzsoVSk6F0efNaOLsek+WC2pVu9n3ZkDnP3nPwRy3Uabufdp8SvExnYQTkCVSY0cfkkb8+pe0TY2wbPv+Hmy3oclD0shVgIEZImQ12zH4u9xigrKydk MHQpcECK Q2mWjSVnz/mipqfAtqGoVgGEh2wdh3xXv/xpz61PIqMMNiNYll20zlUW+BNJok+rdbLeBnL4pkqorhBXGDOUi6yTWrw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Thu, Dec 14, 2023 at 04:48:15PM +0100, Lorenzo Pieralisi wrote: [...] > > AFAICT, the only reason PCI devices can get the blanket treatment of > > Normal-NC at stage-2 is because userspace has a Device-* mapping and can't > > speculatively load from the alias. This feels a bit hacky, and maybe we > > should prioritize an interface for mapping a device into a VM w/o a > > valid userspace mapping. > > FWIW - I have tried to summarize the reasoning behind PCIe devices > Normal-NC default stage-2 safety in a document that I have just realized > now it has become this series cover letter, I don't think the PCI blanket > treatment is related *only* to the current user space mappings (ie > BTW, AFAICS it is also *possible* at present to map a prefetchable BAR through > sysfs with Normal-NC memory attributes in the host at the same time a PCI > device is passed-through to a guest with VFIO - and therefore we have a > dev-nGnRnE stage-1 mapping for it. Don't think anyone does that - what for - > but it is possible and KVM would not know about it). > > Again, FWIW, we were told (source Arm ARM) mismatched aliases concerning > device-XXX vs Normal-NC are not problematic as long as the transactions > issued for the related mappings are independent (and none of the > mappings is cacheable). > > I appreciate this is not enough to give everyone full confidence on > this solution robustness - that's why I wrote that up so that we know > what we are up against and write KVM interfaces accordingly. Apologies, I didn't mean to question what's going on here from the hardware POV. My concern was more from the kernel + user interfaces POV, this all seems to work (specifically for PCI) by maintaining an intentional mismatch between the VFIO stage-1 and KVM stage-2 mappings. If we add more behind-the-scenes tricks to get other MMIO mappings working in the future then this whole interaction will get even hairier. At least if we follow the stage-1 attributes (where possible) then we can document some sort of expected behavior in KVM. The VMM would need know if the device has read side-effects, as the only way to get a Normal-NC mapping in the guest would be to have one at stage-1. Kinda stinks to make the VMM aware of the device, but IMO it is a fundamental limitation of the way we back memslots right now. -- Thanks, Oliver