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Wed, 18 Oct 2023 13:19:51 -0700 (PDT) Received: from ghost ([208.116.208.98]) by smtp.gmail.com with ESMTPSA id pz13-20020ad4550d000000b0065b08bb01afsm208648qvb.124.2023.10.18.13.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 13:19:51 -0700 (PDT) Date: Wed, 18 Oct 2023 13:19:47 -0700 From: Charlie Jenkins To: Emil Renner Berthing Cc: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: Re: [PATCH v4 1/2] riscv: Add remaining module relocations Message-ID: References: <20231017-module_relocations-v4-0-937f5ef316f0@rivosinc.com> <20231017-module_relocations-v4-1-937f5ef316f0@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 923A116002A X-Stat-Signature: 9nxb85ja6q8j1k5ssqgatu6ray1t51jg X-Rspam-User: X-HE-Tag: 1697660392-375907 X-HE-Meta: U2FsdGVkX18drcjVn3G1P9d2iF8aoskqjK52laR1UrlaxXQTSSvjA/fEYr+/H0oPwIxeRimR6SVvh0TL/tF4HDsewBZstReQUpP/tPhR1Q5PYN0lO4hYWfhMTWS9uJTeR0cg8Y84zgpUWgaVpzytgU1Aa0jbiMI2Xv/bOhGkMYBxX7btcJuyTCKLXcQ6MNoE8V5uXuc4D7QUd3eVtxYkF5dN2Sl6k4sTSBgs14LDO7DzcVLLggjcoG/2uZ0CBeciM3CUais59dLMJFL743H/e1a/0kNKaIqHvilj2mKlpRZ8tQfm28F03uy4a+38s9Zxrfbepnk+54hN64pUQeKilhhV818vxuqT2jTfb695NpVcnx2kMznm5IsGPDCLSyRtsmicFF6xMKaP4FWvUGQUUghwvDZ9VzxMCiFy6O5OQK7wxw18Uu/+lzXYn565UEUteGGbCAeczXABYGVX74kY4fSunHxGnK72YTBF2Sj1bQ6w/hl2kX1wfrZi4v0HQrXowZysX+PmysQejn1vuhlNum1+2rIa3ZZnJEpdfzHmHwXend7l+SPMAP5vVyzeoH1dogZNbJxRFiuA5I+ozIff0BseWKcdqbxl4GKxhZdM73NxsUM5+yHzOZYnsnxr6mruRvlo9jH8kvp+HmuKhqWwQE+weqqE6tjvcSVkkOqW+BSht1Zxxi+m3kPq13PNRwVU9ENS3/1nSUuxYBv4wqvgbiRRjj0Fgfan61etsQtAC9Ej9fQz3ZQ0eu1Gmf/vrTxzFYogRTVVyyMqDF8OO2wcs0ezjFnDCKxbLdw2ybJSjpb6i6gpAKEyi/NSvPkY3cyDc2Wg9FdskhmNuZkQnNE6+MjMTtx7yc3Y2bn6HJnFzeJyIQBGEs0z1PTbIPNuDmg1WKR7y1Z/x7gFMmRtMNmI7L1zOS6AmrhZCRKz4xmE8K237QQS2vGXwZceZRueghIjIxap4RsEG916kbm1HHL 37QGBhPo 7xS6rrU1gTM9lpxFsraaBKXd1UlEXBEm52lW0gjQbNRB3fEB3k3iZfhbPocRX4q2ZUv94m3QcC+AY3TPONZVr17efwSPKkEunyV0J+viP1hnP05LlecKZTRZZ7+8PulhPGE+rWCXZLoMlJLkr3Dcl4UQZBF9Hs0FvZJla1c8hLWtpSyB1ikYvpnWauPxHAR7iYXUqKGzm6TG9kptydCZq8rBn/YGWWGbv/8k8tBTR5Ubrjz4r44QlR6mBFjEwcaohRX+tPcZTYkKiusZHTlEUY7dXDztUCyK1hK9WhN7JQTp7GnPghrwXEh228SOgwO67kSSHx0jphGqjjEB0ihZaGkvnlMx1NvMwh0fBdI7BP40RrTdg0Q3bar/Yb+lrIGeEmJiVu9WM2UVwi2N7JzwLiAdEHuvBy2+aqcQsxUXU7fHqB+Ojz0jyJ9tNqurbrhqDyhjPg6C1YWvvlkP9xNf+jLPxGaypYAewHCBl7GZxOSgTombeSj2nI8jH5DUiexx6nM3e9xRhxJQhiddg1jlkwpVM2cyo9eSiZ6HlSoc1R95eUr9lSDyN1CqxhZFXimg8IY1o X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Oct 18, 2023 at 11:38:39AM -0700, Emil Renner Berthing wrote: > Charlie Jenkins wrote: > > On Wed, Oct 18, 2023 at 05:17:44AM -0700, Emil Renner Berthing wrote: > > > Charlie Jenkins wrote: > > > > Add all final module relocations and add error logs explaining the ones > > > > that are not supported. > > > > > > > > Signed-off-by: Charlie Jenkins > > > > --- > > > > arch/riscv/include/uapi/asm/elf.h | 5 +- > > > > arch/riscv/kernel/module.c | 207 +++++++++++++++++++++++++++++++++----- > > > > 2 files changed, 186 insertions(+), 26 deletions(-) > > > > > > > > diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h > > > > index d696d6610231..11a71b8533d5 100644 > > > > --- a/arch/riscv/include/uapi/asm/elf.h > > > > +++ b/arch/riscv/include/uapi/asm/elf.h > > > > @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; > > > > #define R_RISCV_TLS_DTPREL64 9 > > > > #define R_RISCV_TLS_TPREL32 10 > > > > #define R_RISCV_TLS_TPREL64 11 > > > > +#define R_RISCV_IRELATIVE 58 > > > > > > > > /* Relocation types not used by the dynamic linker */ > > > > #define R_RISCV_BRANCH 16 > > > > @@ -81,7 +82,6 @@ typedef union __riscv_fp_state elf_fpregset_t; > > > > #define R_RISCV_ALIGN 43 > > > > #define R_RISCV_RVC_BRANCH 44 > > > > #define R_RISCV_RVC_JUMP 45 > > > > -#define R_RISCV_LUI 46 > > > > #define R_RISCV_GPREL_I 47 > > > > #define R_RISCV_GPREL_S 48 > > > > #define R_RISCV_TPREL_I 49 > > > > @@ -93,6 +93,9 @@ typedef union __riscv_fp_state elf_fpregset_t; > > > > #define R_RISCV_SET16 55 > > > > #define R_RISCV_SET32 56 > > > > #define R_RISCV_32_PCREL 57 > > > > +#define R_RISCV_PLT32 59 > > > > +#define R_RISCV_SET_ULEB128 60 > > > > +#define R_RISCV_SUB_ULEB128 61 > > > > > > > > > > > > #endif /* _UAPI_ASM_RISCV_ELF_H */ > > > > diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c > > > > index 7c651d55fcbd..e860726352ac 100644 > > > > --- a/arch/riscv/kernel/module.c > > > > +++ b/arch/riscv/kernel/module.c > > > > @@ -7,6 +7,7 @@ > > > > #include > > > > #include > > > > #include > > > > +#include > > > > #include > > > > #include > > > > #include > > > > @@ -268,6 +269,12 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, > > > > return -EINVAL; > > > > } > > > > > > > > +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + *(u8 *)location += (u8)v; > > > > + return 0; > > > > +} > > > > + > > > > static int apply_r_riscv_add16_rela(struct module *me, u32 *location, > > > > Elf_Addr v) > > > > { > > > > @@ -289,6 +296,12 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, > > > > return 0; > > > > } > > > > > > > > +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + *(u8 *)location -= (u8)v; > > > > + return 0; > > > > +} > > > > + > > > > static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, > > > > Elf_Addr v) > > > > { > > > > @@ -310,31 +323,149 @@ static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, > > > > return 0; > > > > } > > > > > > > > -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, > > > > - Elf_Addr v) = { > > > > - [R_RISCV_32] = apply_r_riscv_32_rela, > > > > - [R_RISCV_64] = apply_r_riscv_64_rela, > > > > - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, > > > > - [R_RISCV_JAL] = apply_r_riscv_jal_rela, > > > > - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, > > > > - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, > > > > - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, > > > > - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, > > > > - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, > > > > - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, > > > > - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, > > > > - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, > > > > - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, > > > > - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, > > > > - [R_RISCV_CALL] = apply_r_riscv_call_rela, > > > > - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > > > > - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > > > > - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > > > > - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > > > > - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > > > > - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > > > > - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > > > > - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > > > > +static int dynamic_linking_not_supported(struct module *me, u32 *location, > > > > + Elf_Addr v) > > > > +{ > > > > + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", > > > > + me->name, location); > > > > + return -EINVAL; > > > > +} > > > > + > > > > +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", > > > > + me->name, location); > > > > + return -EINVAL; > > > > +} > > > > + > > > > +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + *(u8 *)location = (*location - ((u8)v & 0x3F)) & 0x3F; > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + *(u8 *)location = (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + *(u8 *)location = (u8)v; > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, > > > > + Elf_Addr v) > > > > +{ > > > > + *(u16 *)location = (u16)v; > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, > > > > + Elf_Addr v) > > > > +{ > > > > + *(u32 *)location = (u32)v; > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, > > > > + Elf_Addr v) > > > > +{ > > > > + *(u32 *)location = (u32)v; > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, > > > > + Elf_Addr v) > > > > +{ > > > > + *(u32 *)location = (u32)v; > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_set_uleb128(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + /* > > > > + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by > > > > + * R_RISCV_SUB_ULEB128 so do computation there > > > > + */ > > > > + return 0; > > > > +} > > > > + > > > > +static int apply_r_riscv_sub_uleb128(struct module *me, u32 *location, Elf_Addr v) > > > > +{ > > > > + if (v >= 128) { > > > > + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC = %p\n", > > > > + me->name, (unsigned long)v, location); > > > > + return -EINVAL; > > > > + } > > > > + > > > > + *location = v; > > > > + return 0; > > > > +} > > > > + > > > > +/* > > > > + * Relocations defined in the riscv-elf-psabi-doc. > > > > + * This handles static linking only. > > > > + */ > > > > +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, > > > > + Elf_Addr v) = { > > > > + [R_RISCV_32] = apply_r_riscv_32_rela, > > > > + [R_RISCV_64] = apply_r_riscv_64_rela, > > > > + [R_RISCV_RELATIVE] = dynamic_linking_not_supported, > > > > + [R_RISCV_COPY] = dynamic_linking_not_supported, > > > > + [R_RISCV_JUMP_SLOT] = dynamic_linking_not_supported, > > > > + [R_RISCV_TLS_DTPMOD32] = dynamic_linking_not_supported, > > > > + [R_RISCV_TLS_DTPMOD64] = dynamic_linking_not_supported, > > > > + [R_RISCV_TLS_DTPREL32] = dynamic_linking_not_supported, > > > > + [R_RISCV_TLS_DTPREL64] = dynamic_linking_not_supported, > > > > + [R_RISCV_TLS_TPREL32] = dynamic_linking_not_supported, > > > > + [R_RISCV_TLS_TPREL64] = dynamic_linking_not_supported, > > > > + /* 12-15 undefined */ > > > > + [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, > > > > + [R_RISCV_JAL] = apply_r_riscv_jal_rela, > > > > + [R_RISCV_CALL] = apply_r_riscv_call_rela, > > > > + [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, > > > > + [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, > > > > + [R_RISCV_TLS_GOT_HI20] = tls_not_supported, > > > > + [R_RISCV_TLS_GD_HI20] = tls_not_supported, > > > > + [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, > > > > + [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, > > > > + [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, > > > > + [R_RISCV_HI20] = apply_r_riscv_hi20_rela, > > > > + [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, > > > > + [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, > > > > + [R_RISCV_TPREL_HI20] = tls_not_supported, > > > > + [R_RISCV_TPREL_LO12_I] = tls_not_supported, > > > > + [R_RISCV_TPREL_LO12_S] = tls_not_supported, > > > > + [R_RISCV_TPREL_ADD] = tls_not_supported, > > > > + [R_RISCV_ADD8] = apply_r_riscv_add8_rela, > > > > + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > > > > + [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > > > > + [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > > > > + [R_RISCV_SUB8] = apply_r_riscv_sub8_rela, > > > > + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > > > > + [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > > > > + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > > > > + /* 41-42 reserved for future standard use */ > > > > + [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > > > > + [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, > > > > + [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, > > > > + /* 46-50 reserved for future standard use */ > > > > + [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > > > > + [R_RISCV_SUB6] = apply_r_riscv_sub6_rela, > > > > + [R_RISCV_SET6] = apply_r_riscv_set6_rela, > > > > + [R_RISCV_SET8] = apply_r_riscv_set8_rela, > > > > + [R_RISCV_SET16] = apply_r_riscv_set16_rela, > > > > + [R_RISCV_SET32] = apply_r_riscv_set32_rela, > > > > + [R_RISCV_32_PCREL] = apply_r_riscv_32_pcrel_rela, > > > > + [R_RISCV_IRELATIVE] = dynamic_linking_not_supported, > > > > + [R_RISCV_PLT32] = apply_r_riscv_plt32_rela, > > > > + [R_RISCV_SET_ULEB128] = apply_r_riscv_set_uleb128, > > > > + [R_RISCV_SUB_ULEB128] = apply_r_riscv_sub_uleb128, > > > > + /* 62-191 reserved for future standard use */ > > > > + /* 192-255 nonstandard ABI extensions */ > > > > }; > > > > > > Hi Charlie, > > > > > > This is not a critique of this patch, but all these callbacks take a > > > u32 *location and > > > because of the compressed instructions this pointer may not be > > > aligned, so a lot of > > > the callbacks end up doing unaligned access which may fault to an > > > M-mode handler on > > > some platforms. > > > > > > I once sent a patch to fix this: > > > https://lore.kernel.org/linux-riscv/20220224152456.493365-2-kernel@esmil.dk/ > > > > > > Maybe that's something you want to look into while touching this code anyway. > > > > > > /Emil > > > > Oh nice, I will pick up that patch and change the "native-endian" > > wording to be "little-endian" in the commit. > > Great, thanks. You'll probably also want the reads to be wrapped in > le16_to_cpu() and similar when writing now that it's decided that the parcels > are always in little-endian byteorder. > > /Emil I believe that le16_to_cpu() is only needed when instructions are being modified, and the relocations that only touch data can be left alone. Is this correct? - Charlie > > > > > - Charlie > > > > > > > > > > int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, > > > > @@ -348,6 +479,10 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, > > > > unsigned int i, type; > > > > Elf_Addr v; > > > > int res; > > > > + bool uleb128_set_exists = false; > > > > + u32 *uleb128_set_loc; > > > > + unsigned long uleb128_set_sym_val; > > > > + > > > > > > > > pr_debug("Applying relocate section %u to %u\n", relsec, > > > > sechdrs[relsec].sh_info); > > > > @@ -425,6 +560,28 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, > > > > me->name); > > > > return -EINVAL; > > > > } > > > > + } else if (type == R_RISCV_SET_ULEB128) { > > > > + if (uleb128_set_exists) { > > > > + pr_err("%s: riscv psABI requires the next ULEB128 relocation to come after a R_RISCV_SET_ULEB128 is an R_RISCV_SUB_ULEB128, not another R_RISCV_SET_ULEB128.\n", > > > > + me->name); > > > > + return -EINVAL; > > > > + } > > > > + uleb128_set_exists = true; > > > > + uleb128_set_loc = location; > > > > + uleb128_set_sym_val = > > > > + ((Elf_Sym *)sechdrs[symindex].sh_addr + > > > > + ELF_RISCV_R_SYM(rel[i].r_info)) > > > > + ->st_value + > > > > + rel[i].r_addend; > > > > + } else if (type == R_RISCV_SUB_ULEB128) { > > > > + if (uleb128_set_exists && uleb128_set_loc == location) { > > > > + /* Calculate set and subtraction */ > > > > + v = uleb128_set_sym_val - v; > > > > + } else { > > > > + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with the first R_RISCV_SET_ULEB128 that comes before it. PC = %p\n", > > > > + me->name, location); > > > > + return -EINVAL; > > > > + } > > > > } > > > > > > > > res = handler(me, location, v); > > > > > > > > -- > > > > 2.34.1 > > > > > > > > > > > > _______________________________________________ > > > > linux-riscv mailing list > > > > linux-riscv@lists.infradead.org > > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv