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Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1qP2aS-007a4H-Uu; Thu, 27 Jul 2023 15:07:33 +0000 Date: Thu, 27 Jul 2023 16:07:32 +0100 From: Matthew Wilcox To: Jann Horn Cc: paulmck@kernel.org, Andrew Morton , Linus Torvalds , Peter Zijlstra , Suren Baghdasaryan , linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alan Stern , Andrea Parri , Will Deacon , Boqun Feng , Nicholas Piggin , David Howells , Jade Alglave , Luc Maranget , Akira Yokosawa , Daniel Lustig , Joel Fernandes Subject: Re: [PATCH 0/2] fix vma->anon_vma check for per-VMA locking; fix anon_vma memory ordering Message-ID: References: <20230726214103.3261108-1-jannh@google.com> <31df93bd-4862-432c-8135-5595ffd2bd43@paulmck-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspam-User: X-Stat-Signature: acpkht5p1iq45tr94a99idnoyoj8m8d8 X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 3A0DF10003D X-HE-Tag: 1690470474-826725 X-HE-Meta: U2FsdGVkX1+l11s2x/ihioGEDYQcBHhrGF+93icATnxFT7+P4hUJvVm2jR0OTGV1Fhg0FvigciWBL1luk6rypXOGJlgQE3bfKBXS4sSRhfDRS0s21WOMLYbjRC9gjny71DDLiyEHU+fZOVJxuD+nlt+ePNQ+pmVIbJXjLPeFwD2JDvOTr09w9h3rwM/QXaGtw+7uiApp4m3DvKaiTffLBePI7JD3KSXNxp2U2P+FWiNSJ082oVfaoToN2z3JQ02gE4qPw6uGEj0YJ7MmFOlB4x2xup8lBw0hSWE13LiQK4Z0Jx0abAhlEH2wkNZJVKHdY/o+gE4ZDcAG7HLEuombNPrAFOcY+f0xeIE1YtwO41iLo/nLXXyr+E6ECrt6SG6itzdM6uwgVF9nrF2wPa3S4LQrO9ZR30YnI9+VMbZknz4CPctGjQTcpGQK0vwMGefspjVrCE6U3KaFrATR1CdQCnBIrQEqhACMxylM1lknc/BOm/7h1yxEQxu/X05I0lLYXoFbXxd3NO4+qk9G+1SM1nA9HBuFr9jlHV/gOkET4a0rgs7OXpxTdQ62u6dnaSPFPSeNw8q/EIaQPT5XJqlztFdwh2BxAQrkqq1oqpnWrdXVzav7FDKBpa26Xht3g2mTnB6yu9/DPYhzf6LxSqgRyu3V+TG00muLibIdDJbe4Hx4/6h9fiIxUn+xh+4xPmkZNA4trmZXi2/j8Fctvx89z1ygkaBuKAxbh9yt6yb7JPMn64on1jtWZteOhI5cE807ZwrkdYAlWSVM4oQb6V80jsj1GPrqVGSTR3SASjK7EdLLgTXwI6zTcYW0HoBg0x6vjOCGhQvUUf89HgFgKEYGcUF4lt7o0lEvWaESpkcxaXKdOlHJYDWDyL1FSBUak3+hyTZJ6UYrWlhwvVjM9grvdy1A2OMCCnBWfpbJuzy55RRQMMXHBZlHdyk5uCQKyKF3FFwKJe6qAOcVwXJxbvg FK3h4qJM FmrKKvIn5069ztu8hDoiha6hLeLANjyFe33qNfcZx3k0Ar4ROgE3vqP30pMPXANZNxwj992adVzZ141CtV0xIQLfHurJNpg1RCd3vE51WVAZqCTO5xNG0LEZ74dnT09Xe1AtKz+RrykdQchr0xAGY7rbGqmQwjeIwMg5GPF5FeXwgCvs/7xHsUJo+7NBBWR7xqha7u+I2iWoRNP7ftyNcjT49V/cVYh18MDm8ltQ6KpzJb/UjulKNknxFXiwEov5i68T7 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Thu, Jul 27, 2023 at 04:39:34PM +0200, Jann Horn wrote: > Assume that we are holding some kind of lock that ensures that the > only possible concurrent update to "vma->anon_vma" is that it changes > from a NULL pointer to a non-NULL pointer (using smp_store_release()). > > > if (READ_ONCE(vma->anon_vma) != NULL) { > // we now know that vma->anon_vma cannot change anymore > > // access the same memory location again with a plain load > struct anon_vma *a = vma->anon_vma; > > // this needs to be address-dependency-ordered against one of > // the loads from vma->anon_vma > struct anon_vma *root = a->root; > } > > > Is this fine? If it is not fine just because the compiler might > reorder the plain load of vma->anon_vma before the READ_ONCE() load, > would it be fine after adding a barrier() directly after the > READ_ONCE()? > > I initially suggested using READ_ONCE() for this, and then Linus and > me tried to reason it out and Linus suggested (if I understood him > correctly) that you could make the ugly argument that this works > because loads from the same location will not be reordered by the > hardware. So on anything other than alpha, we'd still have the > required address-dependency ordering because that happens for all > loads, even plain loads, while on alpha, the READ_ONCE() includes a > memory barrier. But that argument is weirdly reliant on > architecture-specific implementation details. > > The other option is to replace the READ_ONCE() with a > smp_load_acquire(), at which point it becomes a lot simpler to show > that the code is correct. Aren't we straining at gnats here? The context of this is handling a page fault, and we used to take an entire rwsem for read. I'm having a hard time caring about "the extra expense" of an unnecessarily broad barrier. Cost of an L3 cacheline miss is in the thousands of cycles. Cost of a barrier is ... tens?