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bh=t6+L9+5TgsgHD5i71rZ4I1fBe7Dw8QjjaTgllTsJASg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=FTfI9Axm5wAnGiuKp4LdSxj2zUd4+mexU7PMy/4ZvlZVAgRtgmuiSsKsrmAW/5JQ3 Nx1+DYd12ijh+vY+2MMUj8nuQgQ5OedPPjhU8pNWewdow+wptVBXcwkFw4Bp4lSpet 2soyzjifgj7cmNt/GzZpy1UpdUFQVMDzDg++8igWTouxWPqD+LEpYiFyE2Xgb2LCBW K42eDy6enK3rwqfFgLk8LIX18zMm2M8KEEACm/dcfJeoqEkQSISLHqOj6ibsLibzP4 k+UaGeEDysFGEkPgfLQLqMgjLo3PqOdrUooNDmr87ylEWSdVmuLT3ijf8vnE5TGh2S CVUBTV2pOGODQ== Date: Wed, 15 Mar 2023 12:10:09 +0200 From: Mike Rapoport To: "Matthew Wilcox (Oracle)" Cc: linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Alexandre Ghiti , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Subject: Re: [PATCH v4 21/36] riscv: Implement the new page table range API Message-ID: References: <20230315051444.3229621-1-willy@infradead.org> <20230315051444.3229621-22-willy@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230315051444.3229621-22-willy@infradead.org> X-Rspamd-Queue-Id: BA9C4C0013 X-Stat-Signature: tdq6dzdzfykd9x1999namupikeazxh6n X-Rspam-User: X-Rspamd-Server: rspam08 X-HE-Tag: 1678875024-682779 X-HE-Meta: U2FsdGVkX1+0iBxQntZbot4a6TQZGCOrrl7ReICNmqG2Yu7BxBvmrwhEFvYrCiu1g6k+75WcxVxe+5XVB6r+exxVOMyD4ViF4tUpNliHk6OZVdJfha567YxQW62uPY4PS9/DGeJ3r+ljPRyAwtVk8RKNmPEY5afAlFy3vlBtv4IeRCFK4jbg/uX791iEp9Vq5ydTOVIGrl4r42d9TzwSE21vCZZ5TQ6lrWQXWemyJxuMfQOAUNz8nMqeT9SMxDkPsXycvr8tsshnCOOu8lb0KDia9hnlC1hPCuhobVmrmYwHKTSQecMJAQF9astHtif1nQIXG6otV2tGgAtbvTp+5mrEh1OiQKeMiyjMvnHbKXpfDktVbSxu02w0r+zxiNY7fPR5zeP/97Toy7noBtQAUr90Iaq+iUnpbXP6iY/bh4ugf6gE3cC2zzfXScp+GZWIaqVT+hJY9OHCryP4FMrvGCxf7gNQyjEIz2Ao1RQlpNvNspgaWs8J4S8lk8vIYFmswmNfAH6UzAs1uv2q/LTNpW0sYhe8wVNjQ25NUttpnElkY8tFji+J9m/ZlQMCjAH63iguHxU9U9jOz+9oS9CJmhFZ+8Mvn2Y29F6aKjjZXMq4gVUeKF4QSCOGNQNFZ66hgrA+y8QMhKDfbuYNfEmFKq2uQHsbeq5POroJlBlmEmeukAqBPoo3ebLnj6TotYIvbjzQZQgjuop76hJCwbZCRuRVBOMb/v1XW7CZlcFk1nSfisNH4NW44KnkKRJWHypbOZanJiR4rG8J23+OxsQEZrkPrGKMcRMWL5BRYUazJlGi1WSvkUvms/tWUU5JLYZmObpdxPXo1F43GAkpoyFVffSlNPH24GIEpxNI2UhzowJtPI6M0Hh4nakyy/UE67EhLgyBIkWlrZrKbl02XIPmYeRVEVSKjhwzjfPCxwJIOT4bcn2Rk3R/+krha8ZexatFjwmdekTXZVyi705H8iD 2cuZL55v 6oQgLnPuomVWL8tgJ2au3BZUbQagjHwnQxg7B43aFsVmV/W0p8hBahKDqWluaXbwUWa1lMGh554Gw66bdSCbfLmXlh9Wy0jtVyZbqP+vvt9bKVhJULyVe0xeJ6vwo7r13czrMx/yjIvc0MqcAX75fgHHW8vydCgMJcJmCn52FqkBkRCFQncsVxZf7AO9f4sw+q0iw8U44LyV+76cIigU9eMpc/+6H7BSi1cUQp7iCrfwCmtAnFu8Gem7JQhWDQKEQSPqsXFOQuWPPGL/xY9CoejZCZ1ndsolBfc+FlWDB8yBNbJl7PTv7H3jmmJMRnS7GenUA6vURYXcZ9Yl65vlanTfmjhEhaDiZ+FAh2+s9cXWT8HuxRCYfDzmLNC39ThdtWTV/G6vxnd1M5x/ta4SJ86EbEjT9can3Ajnwh1Dx5vDIFQSSX38uBhvGnaDclAM6pxOehft4imAdWTSEkNVtXsbpG6HCV2MvyqvZqU8Bk/gVuYzEDcXq8yzbRKvdM5YvIz4T2xTgvLIsemPNAnujTmFrvvgXip4/LNbveCk2HJSDYwd13lPtsebGtA0Pc3fbIKhoKsVqO+PQPMC6Ihw3gaR3z0lCZt+V3I+i X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Mar 15, 2023 at 05:14:29AM +0000, Matthew Wilcox (Oracle) wrote: > Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). > Change the PG_dcache_clean flag from being per-page to per-folio. > > Signed-off-by: Matthew Wilcox (Oracle) > Reviewed-by: Alexandre Ghiti > Cc: Paul Walmsley > Cc: Palmer Dabbelt > Cc: Albert Ou > Cc: linux-riscv@lists.infradead.org Acked-by: Mike Rapoport (IBM) > --- > arch/riscv/include/asm/cacheflush.h | 19 +++++++++---------- > arch/riscv/include/asm/pgtable.h | 26 +++++++++++++++++++------- > arch/riscv/mm/cacheflush.c | 11 ++--------- > 3 files changed, 30 insertions(+), 26 deletions(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index 03e3b95ae6da..10e5e96f09b5 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -15,20 +15,19 @@ static inline void local_flush_icache_all(void) > > #define PG_dcache_clean PG_arch_1 > > -static inline void flush_dcache_page(struct page *page) > +static inline void flush_dcache_folio(struct folio *folio) > { > - /* > - * HugeTLB pages are always fully mapped and only head page will be > - * set PG_dcache_clean (see comments in flush_icache_pte()). > - */ > - if (PageHuge(page)) > - page = compound_head(page); > - > - if (test_bit(PG_dcache_clean, &page->flags)) > - clear_bit(PG_dcache_clean, &page->flags); > + if (test_bit(PG_dcache_clean, &folio->flags)) > + clear_bit(PG_dcache_clean, &folio->flags); > } > +#define flush_dcache_folio flush_dcache_folio > #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 > > +static inline void flush_dcache_page(struct page *page) > +{ > + flush_dcache_folio(page_folio(page)); > +} > + > /* > * RISC-V doesn't have an instruction to flush parts of the instruction cache, > * so instead we just flush the whole thing. > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index b516f3b59616..b077bc8c498c 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -405,8 +405,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) > > > /* Commit new configuration to MMU hardware */ > -static inline void update_mmu_cache(struct vm_area_struct *vma, > - unsigned long address, pte_t *ptep) > +static inline void update_mmu_cache_range(struct vm_area_struct *vma, > + unsigned long address, pte_t *ptep, unsigned int nr) > { > /* > * The kernel assumes that TLBs don't cache invalid entries, but > @@ -415,8 +415,11 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, > * Relying on flush_tlb_fix_spurious_fault would suffice, but > * the extra traps reduce performance. So, eagerly SFENCE.VMA. > */ > - local_flush_tlb_page(address); > + while (nr--) > + local_flush_tlb_page(address + nr * PAGE_SIZE); > } > +#define update_mmu_cache(vma, addr, ptep) \ > + update_mmu_cache_range(vma, addr, ptep, 1) > > #define __HAVE_ARCH_UPDATE_MMU_TLB > #define update_mmu_tlb update_mmu_cache > @@ -456,12 +459,21 @@ static inline void __set_pte_at(struct mm_struct *mm, > set_pte(ptep, pteval); > } > > -static inline void set_pte_at(struct mm_struct *mm, > - unsigned long addr, pte_t *ptep, pte_t pteval) > +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > + pte_t *ptep, pte_t pteval, unsigned int nr) > { > - page_table_check_ptes_set(mm, addr, ptep, pteval, 1); > - __set_pte_at(mm, addr, ptep, pteval); > + page_table_check_ptes_set(mm, addr, ptep, pteval, nr); > + > + for (;;) { > + __set_pte_at(mm, addr, ptep, pteval); > + if (--nr == 0) > + break; > + ptep++; > + addr += PAGE_SIZE; > + pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; > + } > } > +#define set_ptes set_ptes > > static inline void pte_clear(struct mm_struct *mm, > unsigned long addr, pte_t *ptep) > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > index fcd6145fbead..e36a851e5788 100644 > --- a/arch/riscv/mm/cacheflush.c > +++ b/arch/riscv/mm/cacheflush.c > @@ -81,16 +81,9 @@ void flush_icache_mm(struct mm_struct *mm, bool local) > #ifdef CONFIG_MMU > void flush_icache_pte(pte_t pte) > { > - struct page *page = pte_page(pte); > + struct folio *folio = page_folio(pte_page(pte)); > > - /* > - * HugeTLB pages are always fully mapped, so only setting head page's > - * PG_dcache_clean flag is enough. > - */ > - if (PageHuge(page)) > - page = compound_head(page); > - > - if (!test_bit(PG_dcache_clean, &page->flags)) { > + if (!test_bit(PG_dcache_clean, &folio->flags)) { > flush_icache_all(); > set_bit(PG_dcache_clean, &page->flags); > } > -- > 2.39.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Sincerely yours, Mike.