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bh=dOgzlBLPlOS+XYasJ+6eJlX1/dEnbvS4fGafOnUfsz8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=AByWUKAVZiITmU8Swud8hn6PhHc/swNFS21og02GUGdjC864s3RfOkwOWi7mGhwka Vn9nDg/PAA8PQIUcLRHMVxBI3OL0Zh6j14sIHjGlVQythjKtVeybJ6CCVDNXEMqrPF FQL3GpKM/skJJ6kzb1OcBAhc+uZtoPnUomEfbw9xW7NaKze7EXuT1qxXiRxYcJ8Sxj gNEoXpKSYaZL8N+HE3rOTlYQZAfPDzf/tcZKFcDrl9Fzr9u1cgMCf5AgAlrr8Sb8eA H02/TD16cAijVy2/josMh83yvCBoiSqW7/Yw30d+S/50Aphl/Ni5YlNAjuCfahxOo6 LrK18vjSTHW7Q== Date: Fri, 3 Mar 2023 13:56:36 +0200 From: Mike Rapoport To: "Matthew Wilcox (Oracle)" Cc: linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-ia64@vger.kernel.org Subject: Re: [PATCH v3 11/34] ia64: Implement the new page table range API Message-ID: References: <20230228213738.272178-1-willy@infradead.org> <20230228213738.272178-12-willy@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230228213738.272178-12-willy@infradead.org> X-Stat-Signature: nd1p8c4chbwqo3bnbqcz41oo9fzorare X-Rspam-User: X-Rspamd-Queue-Id: 5EC2B40010 X-Rspamd-Server: rspam06 X-HE-Tag: 1677844611-969122 X-HE-Meta: U2FsdGVkX1/MNQQe0Kc4DxN2sqRB9IM8+Lu0bIRZbRg2O/3MvrF5DD7EXViVkd1Q+6NH9J6O0CZDzwmfz7xchQEE2ARKFU+ydPjNff/HCL8hQ1PfyJFfslIGvF5zwZFnjcAeAox3u3DOUIESirHOEY0cDupdZJo3GbZe1Gzfg53IKC14oRqEBe/WDxeB6A1dIwXRmzlPo3ncJzgtgLchXK6bf2g8SbpFz7vSXhHLTic28D5slrXRipyH1BSqmoR1pemQcj2BgiDdVJ5AmZTMesA+dJk9sE6MLff1YQ4FqP9YTaVHqnsnLzrvH0WI8KKjF3wbR2svWqY6Ix+S4M4Qu7dt6gFqJM7wX4nz1xhTNHdUSJP3u7R8zwky4uiIIegBQItym9ZcLTG18PK/CdAj763Ic4ThkZrof/6oRTip5TE7lMMLhCVDB6TXoBN0ruZEzVV87lXa1FQSdkoSYnMHcCN0XXpN/OX/BtRpZ/J9AUTScBwbt7R71n3KXe2qk5REkWdP2LcOQXp3c9keY4cz8UQ14jjyIXxm6gIrPxxmbdY3lTpdC0trJqiBEER4IY7DG8vrD73iEh+CZQxS4lwzdY5s39ER54mgGvlny0gepqVyDFSMJGoimSDbM/3pwOM9qBaLeR1bkxMsX1TAJ7ZEr4FgWN0O9JNJb+VdcLB+qe6+dGOKSoCGUe83wITAlDr0avQR5bXA3fow/ocTZaa5dELgQHhh7NiEDbXe6Ecr7aeP11KQXblcQFMQcF/U2B1EuVv1Za9XSomAh0Vz0dBArIL+HkcRK7Gwus9S/c5+IUEkc3q5969fU7eoD3M2pVsxRHNANbBZgz8yBqCGypA3QuQY+Slwrx9qKfB0LRkzJezb9JT069PLKtsccifMVBkeTzpXuD/+kiCbbHqsrsqiIAtqq/klhucz5g7XFu+u3Fve3iickdWFWbjDqKduguiV+GsGMGamF9oG/Wha4bd 5Dm65VtK OuSs04VDiagGTko4Z5eLeNNmJLKas132wAojsQknniym2monbAZYFZXoN59tidXUkNlZuvY+Lf6QNAsUjuGhkSxpsIYxCbpudlbiFS+T5ZOBqUsuQXX6AWiLyptZ8/OiK1FEU+OHkMTZ3JELrnD98yzMJSw2DBPkC7ysMgYf6tL2eWbZCX5k84dFMcbzwzi4TmbMAbzX3tVDp3sulO/x7Qt18mCDsZRK1Ovn/31ceHB3sFv08Vk795m1cPCWfsdukgi9Rrzz/mBKLqRG8AP0afULQyUvVxngvoXuRz2a8dOZuM0kwQSVLOgCd2XngZcvoUbuPDugRU/yI3fK57Dk6kzSR5+25w52J8itqZbNIz3Y1Z80WTG+Z+LzMhObQpZ87EY2jnD64yrH2U0lVTrHyfkRHvvEg5oLJNvy9oSzp8b/RhPg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, Feb 28, 2023 at 09:37:14PM +0000, Matthew Wilcox (Oracle) wrote: > Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). > Change the PG_arch_1 (aka PG_dcache_clean) flag from being per-page to > per-folio, which makes arch_dma_mark_clean() and mark_clean() a little > more exciting. > > Signed-off-by: Matthew Wilcox (Oracle) > Cc: linux-ia64@vger.kernel.org > --- > arch/ia64/hp/common/sba_iommu.c | 26 +++++++++++++++----------- > arch/ia64/include/asm/cacheflush.h | 14 ++++++++++---- > arch/ia64/include/asm/pgtable.h | 14 +++++++++++++- > arch/ia64/mm/init.c | 29 +++++++++++++++++++---------- > 4 files changed, 57 insertions(+), 26 deletions(-) > > diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c > index 8ad6946521d8..48d475f10003 100644 > --- a/arch/ia64/hp/common/sba_iommu.c > +++ b/arch/ia64/hp/common/sba_iommu.c > @@ -798,22 +798,26 @@ sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba) > #endif > > #ifdef ENABLE_MARK_CLEAN > -/** > +/* > * Since DMA is i-cache coherent, any (complete) pages that were written via > * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to > * flush them when they get mapped into an executable vm-area. > */ > -static void > -mark_clean (void *addr, size_t size) > +static void mark_clean(void *addr, size_t size) > { > - unsigned long pg_addr, end; > - > - pg_addr = PAGE_ALIGN((unsigned long) addr); > - end = (unsigned long) addr + size; > - while (pg_addr + PAGE_SIZE <= end) { > - struct page *page = virt_to_page((void *)pg_addr); > - set_bit(PG_arch_1, &page->flags); > - pg_addr += PAGE_SIZE; > + struct folio *folio = virt_to_folio(addr); > + ssize_t left = size; > + size_t offset = offset_in_folio(folio, addr); > + > + if (offset) { > + left -= folio_size(folio) - offset; > + folio = folio_next(folio); > + } > + > + while (left >= folio_size(folio)) { > + set_bit(PG_arch_1, &folio->flags); > + left -= folio_size(folio); > + folio = folio_next(folio); > } > } > #endif > diff --git a/arch/ia64/include/asm/cacheflush.h b/arch/ia64/include/asm/cacheflush.h > index 708c0fa5d975..eac493fa9e0d 100644 > --- a/arch/ia64/include/asm/cacheflush.h > +++ b/arch/ia64/include/asm/cacheflush.h > @@ -13,10 +13,16 @@ > #include > > #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 > -#define flush_dcache_page(page) \ > -do { \ > - clear_bit(PG_arch_1, &(page)->flags); \ > -} while (0) > +static inline void flush_dcache_folio(struct folio *folio) > +{ > + clear_bit(PG_arch_1, &folio->flags); > +} > +#define flush_dcache_folio flush_dcache_folio > + > +static inline void flush_dcache_page(struct page *page) > +{ > + flush_dcache_folio(page_folio(page)); > +} > > extern void flush_icache_range(unsigned long start, unsigned long end); > #define flush_icache_range flush_icache_range > diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h > index 21c97e31a28a..0c2be4ea664b 100644 > --- a/arch/ia64/include/asm/pgtable.h > +++ b/arch/ia64/include/asm/pgtable.h > @@ -303,7 +303,18 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) > *ptep = pteval; > } > > -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) > +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > + pte_t *ptep, pte_t pte, unsigned int nr) > +{ > + for (;;) { > + set_pte(ptep, pte); > + if (--nr == 0) > + break; > + ptep++; > + pte_val(pte) += PAGE_SIZE; > + } > +} > +#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, add, ptep, pte, 1) > > /* > * Make page protection values cacheable, uncacheable, or write- > @@ -396,6 +407,7 @@ pte_same (pte_t a, pte_t b) > return pte_val(a) == pte_val(b); > } > > +#define update_mmu_cache_range(vma, address, ptep, nr) do { } while (0) > #define update_mmu_cache(vma, address, ptep) do { } while (0) > > extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; > diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c > index 7f5353e28516..12aef25944aa 100644 > --- a/arch/ia64/mm/init.c > +++ b/arch/ia64/mm/init.c > @@ -50,30 +50,39 @@ void > __ia64_sync_icache_dcache (pte_t pte) > { > unsigned long addr; > - struct page *page; > + struct folio *folio; > > - page = pte_page(pte); > - addr = (unsigned long) page_address(page); > + folio = page_folio(pte_page(pte)); > + addr = (unsigned long)folio_address(folio); > > - if (test_bit(PG_arch_1, &page->flags)) > + if (test_bit(PG_arch_1, &folio->flags)) > return; /* i-cache is already coherent with d-cache */ > > - flush_icache_range(addr, addr + page_size(page)); > - set_bit(PG_arch_1, &page->flags); /* mark page as clean */ > + flush_icache_range(addr, addr + folio_size(folio)); > + set_bit(PG_arch_1, &folio->flags); /* mark page as clean */ > } > > /* > - * Since DMA is i-cache coherent, any (complete) pages that were written via > + * Since DMA is i-cache coherent, any (complete) folios that were written via > * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to > * flush them when they get mapped into an executable vm-area. > */ > void arch_dma_mark_clean(phys_addr_t paddr, size_t size) > { > - unsigned long pfn = PHYS_PFN(paddr); > + struct folio *folio = page_folio(phys_to_page(paddr)); > + ssize_t left = size; > + size_t offset = offset_in_folio(folio, paddr); Build of defconfig failed miserably for me without this: diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c index 12aef25944aa..0775e7870257 100644 --- a/arch/ia64/mm/init.c +++ b/arch/ia64/mm/init.c @@ -69,7 +69,8 @@ __ia64_sync_icache_dcache (pte_t pte) */ void arch_dma_mark_clean(phys_addr_t paddr, size_t size) { - struct folio *folio = page_folio(phys_to_page(paddr)); + unsigned long pfn = __phys_to_pfn(paddr); + struct folio *folio = page_folio(pfn_to_page(pfn)); ssize_t left = size; size_t offset = offset_in_folio(folio, paddr); > > - do { > + if (offset) { > + left -= folio_size(folio) - offset; > + folio = folio_next(folio); > + } > + > + while (left >= (ssize_t)folio_size(folio)) { > set_bit(PG_arch_1, &pfn_to_page(pfn)->flags); > - } while (++pfn <= PHYS_PFN(paddr + size - 1)); > + left -= folio_size(folio); > + folio = folio_next(folio); > + } > } > > inline void > -- > 2.39.1 > -- Sincerely yours, Mike.