From: Alison Schofield <alison.schofield@intel.com>
To: shiju.jose@huawei.com
Cc: linux-cxl@vger.kernel.org, dan.j.williams@intel.com,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, david@redhat.com, Vilas.Sridharan@amd.com,
linux-edac@vger.kernel.org, linux-acpi@vger.kernel.org,
linux-mm@kvack.org, linux-kernel@vger.kernel.org, bp@alien8.de,
tony.luck@intel.com, rafael@kernel.org, lenb@kernel.org,
mchehab@kernel.org, leo.duran@amd.com, Yazen.Ghannam@amd.com,
rientjes@google.com, jiaqiyan@google.com, Jon.Grimm@amd.com,
dave.hansen@linux.intel.com, naoya.horiguchi@nec.com,
james.morse@arm.com, jthoughton@google.com,
somasundaram.a@hpe.com, erdemaktas@google.com, pgonda@google.com,
duenwen@google.com, gthelen@google.com,
wschwartz@amperecomputing.com, dferguson@amperecomputing.com,
wbs@os.amperecomputing.com, nifan.cxl@gmail.com,
tanxiaofei@huawei.com, prime.zeng@hisilicon.com,
roberto.sassu@huawei.com, kangkang.shen@futurewei.com,
wanghuiqiang@huawei.com, linuxarm@huawei.com
Subject: Re: [PATCH 6/8] cxl: Support for finding memory operation attributes from the current boot
Date: Fri, 7 Mar 2025 18:09:20 -0800 [thread overview]
Message-ID: <Z8um0DcVyKra2vYa@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250227223816.2036-7-shiju.jose@huawei.com>
On Thu, Feb 27, 2025 at 10:38:13PM +0000, shiju.jose@huawei.com wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
snip
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> new file mode 100644
> index 000000000000..65994eec1037
> --- /dev/null
> +++ b/drivers/cxl/core/ras.c
> @@ -0,0 +1,151 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * CXL RAS driver.
> + *
> + * Copyright (c) 2025 HiSilicon Limited.
> + *
> + */
Please use the same 2-line header format as other .c files in this
directory.
Why is this GPL-2.0-or-later when all others are GPL-2.0-only?
next prev parent reply other threads:[~2025-03-08 2:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 22:38 [PATCH 0/8] cxl: support CXL memory RAS features shiju.jose
2025-02-27 22:38 ` [PATCH 1/8] cxl: Add helper function to retrieve a feature entry shiju.jose
2025-03-07 0:55 ` Jonathan Cameron
2025-03-07 1:58 ` Fan Ni
2025-03-07 19:19 ` Alison Schofield
2025-03-10 18:15 ` Shiju Jose
2025-03-10 20:28 ` Alison Schofield
2025-03-11 9:51 ` Shiju Jose
2025-02-27 22:38 ` [PATCH 2/8] cxl/memfeature: Add CXL memory device patrol scrub control feature shiju.jose
2025-03-07 1:39 ` Dan Williams
2025-03-07 19:53 ` Alison Schofield
2025-02-27 22:38 ` [PATCH 3/8] cxl/memfeature: Add CXL memory device ECS " shiju.jose
2025-03-07 1:01 ` Jonathan Cameron
2025-03-07 2:46 ` Fan Ni
2025-03-08 1:48 ` Alison Schofield
2025-02-27 22:38 ` [PATCH 4/8] cxl/mbox: Add support for PERFORM_MAINTENANCE mailbox command shiju.jose
2025-02-27 22:38 ` [PATCH 5/8] cxl/region: Add helper function to determine memory is online shiju.jose
2025-03-07 22:01 ` Alison Schofield
2025-02-27 22:38 ` [PATCH 6/8] cxl: Support for finding memory operation attributes from the current boot shiju.jose
2025-03-08 2:09 ` Alison Schofield [this message]
2025-02-27 22:38 ` [PATCH 7/8] cxl/memfeature: Add CXL memory device soft PPR control feature shiju.jose
2025-03-07 1:04 ` Jonathan Cameron
2025-02-27 22:38 ` [PATCH 8/8] cxl/memfeature: Add CXL memory device memory sparing " shiju.jose
2025-03-07 1:11 ` Jonathan Cameron
2025-03-07 23:32 ` Alison Schofield
2025-03-08 2:35 ` Alison Schofield
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