Re: [PATCH V5 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9)

[Deepak Gupta <debug@rivosinc.com>]

Sorry for the late response.

On Tue, Feb 11, 2025 at 04:05:02PM +0800, Chunyan Zhang wrote:
>On Tue, 11 Feb 2025 at 12:01, Deepak Gupta <debug@rivosinc.com> wrote:
>>
>> On Tue, Feb 11, 2025 at 09:20:22AM +0800, Chunyan Zhang wrote:
>> >On Thu, 30 Jan 2025 at 16:42, Björn Töpel <bjorn@kernel.org> wrote:
>> >>
>> >> Chunyan Zhang <zhangchunyan@iscas.ac.cn> writes:
>> >>
>> >> > The PTE bit(9) on RISC-V is reserved for software, it is used by devmap
>> >> > now which has to be disabled if we want to use bit(9) for other features,
>> >> > since there's no more free PTE bit on RISC-V now.
>> >> >
>> >> > So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as
>> >> > the build condition of devmap definitions.
>> >>
>> >> Heads-up: It seems like Alistair's series [1] that removes the devmap
>> >> PTE bit will most likely land in 6.15.
>> >
>> >Yes, I've been keeping an eye on Alistair's series, intended to update
>> >this patchset after Alistair's patch that removes the devmap PTE bit
>> >got merged.
>>
>> Please keep in mind that even after claiming back devmap PTE SW bit, a compile
>> time decision to select between uffd-wp and soft-dirty is not desirable.
>
>Yes, I agree. I've read your aother email. I also hope we can have
>more RSW bits to use. So should we add uffd-wp and soft-dirty support
>on RISC-V until we have two RSW bits for these two functions? Is an
>undesirable solution better than no solution for now?

Problem is that this undesirable solution doesn't solve anything for *most* users.
Kernel can't deviate from providing functionality (which is actually arch-agnostic) to
user mode depending on the architecture.

>I can optimize the code when we have more free RSW bits, that's not hard.


We got 3 use cases,

- pfnmap/pte_special
- uffd-wp
- softdirty

4th one for devmap, I hope we don't need to do it. Should get it back.
https://lore.kernel.org/lkml/cover.95ff0627bc727f2bae44bea4c00ad7a83fbbcfac.1739941374.git-series.apopple@nvidia.com/#r
It looks like any work there would be wasted time.

There is a (fast track) proposal out there to get 2 more RSW bits.
https://lists.riscv.org/g/tech-privileged/message/2268

I hope it gets ratified soon. We will have proper solution to this problem then.