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From: Peter Xu <peterx@redhat.com>
To: Alistair Popple <apopple@nvidia.com>
Cc: "Huang, Ying" <ying.huang@intel.com>,
	Nadav Amit <nadav.amit@gmail.com>,
	huang ying <huang.ying.caritas@gmail.com>,
	Linux MM <linux-mm@kvack.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	LKML <linux-kernel@vger.kernel.org>,
	"Sierra Guiza, Alejandro (Alex)" <alex.sierra@amd.com>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	Jason Gunthorpe <jgg@nvidia.com>,
	John Hubbard <jhubbard@nvidia.com>,
	David Hildenbrand <david@redhat.com>,
	Ralph Campbell <rcampbell@nvidia.com>,
	Matthew Wilcox <willy@infradead.org>,
	Karol Herbst <kherbst@redhat.com>, Lyude Paul <lyude@redhat.com>,
	Ben Skeggs <bskeggs@redhat.com>,
	Logan Gunthorpe <logang@deltatee.com>,
	paulus@ozlabs.org, linuxppc-dev@lists.ozlabs.org,
	stable@vger.kernel.org
Subject: Re: [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page
Date: Wed, 24 Aug 2022 16:25:44 -0400	[thread overview]
Message-ID: <YwaJSBnp2eyMlkjw@xz-m1.local> (raw)
In-Reply-To: <87czcqiecd.fsf@nvdebian.thelocal>

On Wed, Aug 24, 2022 at 11:56:25AM +1000, Alistair Popple wrote:
> >> Still I don't know whether there'll be any side effect of having stall tlbs
> >> in !present ptes because I'm not familiar enough with the private dev swap
> >> migration code.  But I think having them will be safe, even if redundant.
> 
> What side-effect were you thinking of? I don't see any issue with not
> TLB flushing stale device-private TLBs prior to the migration because
> they're not accessible anyway and shouldn't be in any TLB.

Sorry to be misleading, I never meant we must add them.  As I said it's
just that I don't know the code well so I don't know whether it's safe to
not have it.

IIUC it's about whether having stall system-ram stall tlb in other
processor would matter or not here.  E.g. some none pte that this code
collected (boosted both "cpages" and "npages" for a none pte) could have
stall tlb in other cores that makes the page writable there.

When I said I'm not familiar with the code, it's majorly about one thing I
never figured out myself, in that migrate_vma_collect_pmd() has this
optimization to trylock on the page, collect if it succeeded:

  /*
   * Optimize for the common case where page is only mapped once
   * in one process. If we can lock the page, then we can safely
   * set up a special migration page table entry now.
   */
   if (trylock_page(page)) {
          ...
   } else {
          put_page(page);
          mpfn = 0;
   }

But it's kind of against a pure "optimization" in that if trylock failed,
we'll clear the mpfn so the src[i] will be zero at last.  Then will we
directly give up on this page, or will we try to lock_page() again
somewhere?

The future unmap op is also based on this "cpages", not "npages":

	if (args->cpages)
		migrate_vma_unmap(args);

So I never figured out how this code really works.  It'll be great if you
could shed some light to it.

Thanks,

-- 
Peter Xu



  reply	other threads:[~2022-08-24 20:25 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-16  7:39 Alistair Popple
2022-08-16  7:39 ` [PATCH v2 2/2] selftests/hmm-tests: Add test for dirty bits Alistair Popple
2022-08-16  8:10 ` [PATCH v2 1/2] mm/migrate_device.c: Copy pte dirty bit to page huang ying
2022-08-16 20:35   ` Peter Xu
2022-08-17  1:49     ` Alistair Popple
2022-08-17  2:45       ` Peter Xu
2022-08-17  5:41         ` Alistair Popple
2022-08-17  7:17           ` Huang, Ying
2022-08-17  9:41             ` Nadav Amit
2022-08-17 19:27               ` Peter Xu
2022-08-18  6:34                 ` Huang, Ying
2022-08-18 14:44                   ` Peter Xu
2022-08-19  2:51                     ` Huang, Ying
2022-08-24  1:56                       ` Alistair Popple
2022-08-24 20:25                         ` Peter Xu [this message]
2022-08-24 20:48                           ` Peter Xu
2022-08-25  0:42                             ` Alistair Popple
2022-08-25  1:24                               ` Alistair Popple
2022-08-25 15:04                                 ` Peter Xu
2022-08-25 22:09                                   ` Alistair Popple
2022-08-25 23:36                                     ` Peter Xu
2022-08-25 14:40                               ` Peter Xu
2022-08-18  5:59               ` Huang, Ying
2022-08-17 19:07           ` Peter Xu
2022-08-17  1:38   ` Alistair Popple

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