From: Peter Zijlstra <peterz@infradead.org>
To: Huang Ying <ying.huang@intel.com>
Cc: Mel Gorman <mgorman@suse.de>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
Feng Tang <feng.tang@intel.com>,
Andrew Morton <akpm@linux-foundation.org>,
Michal Hocko <mhocko@suse.com>, Rik van Riel <riel@surriel.com>,
Mel Gorman <mgorman@techsingularity.net>,
Dave Hansen <dave.hansen@linux.intel.com>,
Yang Shi <shy828301@gmail.com>, Zi Yan <ziy@nvidia.com>,
Wei Xu <weixugc@google.com>, osalvador <osalvador@suse.de>,
Shakeel Butt <shakeelb@google.com>,
Hasan Al Maruf <hasanalmaruf@fb.com>
Subject: Re: [PATCH -V10 RESEND 0/6] NUMA balancing: optimize memory placement for memory tiering system
Date: Wed, 12 Jan 2022 17:10:23 +0100 [thread overview]
Message-ID: <Yd79b6PptQMNzDRw@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20211207022757.2523359-1-ying.huang@intel.com>
On Tue, Dec 07, 2021 at 10:27:51AM +0800, Huang Ying wrote:
> After commit c221c0b0308f ("device-dax: "Hotplug" persistent memory
> for use like normal RAM"), the PMEM could be used as the
> cost-effective volatile memory in separate NUMA nodes. In a typical
> memory tiering system, there are CPUs, DRAM and PMEM in each physical
> NUMA node. The CPUs and the DRAM will be put in one logical node,
> while the PMEM will be put in another (faked) logical node.
So what does a system like that actually look like, SLIT table wise, and
how does that affect init_numa_topology_type() ?
next prev parent reply other threads:[~2022-01-12 16:10 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-07 2:27 Huang Ying
2021-12-07 2:27 ` [PATCH -V10 RESEND 1/6] NUMA Balancing: add page promotion counter Huang Ying
2021-12-07 6:05 ` Hasan Al Maruf
2021-12-08 2:16 ` Huang, Ying
2021-12-17 7:25 ` Baolin Wang
2021-12-07 2:27 ` [PATCH -V10 RESEND 2/6] NUMA balancing: optimize page placement for memory tiering system Huang Ying
2021-12-07 6:36 ` Hasan Al Maruf
2021-12-08 3:16 ` Huang, Ying
2021-12-17 7:35 ` Baolin Wang
2021-12-07 2:27 ` [PATCH -V10 RESEND 3/6] memory tiering: skip to scan fast memory Huang Ying
2021-12-17 7:41 ` Baolin Wang
2021-12-07 2:27 ` [PATCH -V10 RESEND 4/6] memory tiering: hot page selection with hint page fault latency Huang Ying
2021-12-07 2:27 ` [PATCH -V10 RESEND 5/6] memory tiering: rate limit NUMA migration throughput Huang Ying
2021-12-07 2:27 ` [PATCH -V10 RESEND 6/6] memory tiering: adjust hot threshold automatically Huang Ying
2022-01-12 16:10 ` Peter Zijlstra [this message]
2022-01-13 7:19 ` [PATCH -V10 RESEND 0/6] NUMA balancing: optimize memory placement for memory tiering system Huang, Ying
2022-01-13 9:49 ` Peter Zijlstra
[not found] ` <87o84fu9f3.fsf@yhuang6-desk2.ccr.corp.intel.com>
2022-01-13 13:00 ` Peter Zijlstra
2022-01-13 13:13 ` Huang, Ying
2022-01-13 14:24 ` Huang, Ying
2022-01-14 5:24 ` Huang, Ying
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