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Wed, 24 Mar 2021 02:56:45 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id a131sm1771261wmc.48.2021.03.24.02.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 02:56:45 -0700 (PDT) Date: Wed, 24 Mar 2021 10:56:43 +0100 From: Daniel Vetter To: Thomas =?iso-8859-1?Q?Hellstr=F6m_=28Intel=29?= Cc: Jason Gunthorpe , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mm@kvack.org, Andrew Morton , Christian Koenig Subject: Re: [RFC PATCH 1/2] mm,drm/ttm: Block fast GUP to TTM huge pages Message-ID: Mail-Followup-To: Thomas =?iso-8859-1?Q?Hellstr=F6m_=28Intel=29?= , Jason Gunthorpe , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mm@kvack.org, Andrew Morton , Christian Koenig References: <20210321184529.59006-1-thomas_os@shipmail.org> <20210321184529.59006-2-thomas_os@shipmail.org> <314fc020-d243-dbf0-acb3-ecfcc9c2443c@shipmail.org> <20210323163715.GJ2356281@nvidia.com> <5824b731-ca6a-92fd-e314-d986b6a7b101@shipmail.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <5824b731-ca6a-92fd-e314-d986b6a7b101@shipmail.org> X-Operating-System: Linux phenom 5.7.0-1-amd64 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 7FF46C0007CA X-Stat-Signature: cgckpkt3qgrp4d1hgn1z1ep83iyf5rm6 Received-SPF: none (ffwll.ch>: No applicable sender policy available) receiver=imf06; identity=mailfrom; envelope-from=""; helo=mail-wr1-f49.google.com; client-ip=209.85.221.49 X-HE-DKIM-Result: pass/pass X-HE-Tag: 1616579806-933580 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellstr=F6m (Intel) wrot= e: >=20 > On 3/23/21 5:37 PM, Jason Gunthorpe wrote: > > On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellstr=F6m (Intel) = wrote: > >=20 > > > > > @@ -210,6 +211,20 @@ static vm_fault_t ttm_bo_vm_insert_huge(st= ruct vm_fault *vmf, > > > > > if ((pfn & (fault_page_size - 1)) !=3D 0) > > > > > goto out_fallback; > > > > > + /* > > > > > + * Huge entries must be special, that is marking them as devm= ap > > > > > + * with no backing device map range. If there is a backing > > > > > + * range, Don't insert a huge entry. > > > > > + * If this check turns out to be too much of a performance hi= t, > > > > > + * we can instead have drivers indicate whether they may have > > > > > + * backing device map ranges and if not, skip this lookup. > > > > > + */ > > > > I think we can do this statically: > > > > - if it's system memory we know there's no devmap for it, and we = do the > > > > trick to block gup_fast > > > Yes, that should work. > > > > - if it's iomem, we know gup_fast wont work anyway if don't set P= FN_DEV, > > > > so might as well not do that > > > I think gup_fast will unfortunately mistake a huge iomem page for a= n > > > ordinary page and try to access a non-existant struct page for it, = unless we > > > do the devmap trick. > > >=20 > > > And the lookup would then be for the rare case where a driver would= have > > > already registered a dev_pagemap for an iomem area which may also b= e mapped > > > through TTM (like the patch from Felix a couple of weeks ago). If a= driver > > > can promise not to do that, then we can safely remove the lookup. > > Isn't the devmap PTE flag arch optional? Does this fall back to not > > using huge pages on arches that don't support it? >=20 > Good point. No, currently it's only conditioned on transhuge page suppo= rt. > Need to condition it on also devmap support. >=20 > >=20 > > Also, I feel like this code to install "pte_special" huge pages does > > not belong in the drm subsystem.. >=20 > I could add helpers in huge_memory.c: >=20 > vmf_insert_pfn_pmd_prot_special() and > vmf_insert_pfn_pud_prot_special() The somewhat annoying thing is that we'd need an error code so we fall back to pte fault handling. That's at least my understanding of how pud/pmd fault handling works. Not sure how awkward that is going to be with the overall fault handling flow. But aside from that I think this makes tons of sense. -Daniel --=20 Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch