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charset=utf-8 Content-Disposition: inline In-Reply-To: <85DAADF4-2537-40BD-8580-A57C201FF5F3@gmail.com> Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Sat, Jan 16, 2021 at 11:32:22PM -0800, Nadav Amit wrote: > > On Jan 16, 2021, at 8:41 PM, Yu Zhao wrote: > >=20 > > On Tue, Jan 12, 2021 at 09:43:38PM +0000, Will Deacon wrote: > >> On Tue, Jan 12, 2021 at 12:38:34PM -0800, Nadav Amit wrote: > >>>> On Jan 12, 2021, at 11:56 AM, Yu Zhao wrote: > >>>> On Tue, Jan 12, 2021 at 11:15:43AM -0800, Nadav Amit wrote: > >>>>> I will send an RFC soon for per-table deferred TLB flushes tracki= ng. > >>>>> The basic idea is to save a generation in the page-struct that tr= acks > >>>>> when deferred PTE change took place, and track whenever a TLB flu= sh > >>>>> completed. In addition, other users - such as mprotect - would us= e > >>>>> the tlb_gather interface. > >>>>>=20 > >>>>> Unfortunately, due to limited space in page-struct this would onl= y > >>>>> be possible for 64-bit (and my implementation is only for x86-64)= . > >>>>=20 > >>>> I don't want to discourage you but I don't think this would end up > >>>> well. PPC doesn't necessarily follow one-page-struct-per-table rul= e, > >>>> and I've run into problems with this before while trying to do > >>>> something similar. > >>>=20 > >>> Discourage, discourage. Better now than later. > >>>=20 > >>> It will be relatively easy to extend the scheme to be per-VMA inste= ad of > >>> per-table for architectures that prefer it this way. It does requir= e > >>> TLB-generation tracking though, which Andy only implemented for x86= , so I > >>> will focus on x86-64 right now. > >>=20 > >> Can you remind me of what we're missing on arm64 in this area, pleas= e? I'm > >> happy to help get this up and running once you have something I can = build > >> on. > >=20 > > I noticed arm/arm64 don't support ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH. > > Would it be something worth pursuing? Arm has been using mm_cpumask, > > so it might not be too difficult I guess? >=20 > [ +Mel Gorman who implemented ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH ] >=20 > IIUC, there are at least two bugs in x86 implementation. >=20 > First, there is a missing memory barrier in tlbbatch_add_mm() between > inc_mm_tlb_gen() and the read of mm_cpumask(). In arch_tlbbatch_add_mm()? inc_mm_tlb_gen() has builtin barrier as its comment says -- atomic update ops that return values are also full memory barriers. > Second, try_to_unmap_flush() clears flush_required after flushing. Anot= her > thread can call set_tlb_ubc_flush_pending() after the flush and before > flush_required is cleared, and the indication that a TLB flush is pendi= ng > can be lost. This isn't a problem either because flush_required is per thread. > I am working on addressing these issues among others, but, as you alrea= dy > saw, I am a bit slow. >=20 > On a different but related topic: Another thing that I noticed that Arm= does > not do is batching TLB flushes across VMAs. Since Arm does not have its= own > tlb_end_vma(), it uses the default tlb_end_vma(), which flushes each VM= A > separately. Peter Zijlstra=E2=80=99s comment says that there are advant= ages in > flushing each VMA separately, but I am not sure it is better or intenti= onal > (especially since x86 does not do so). >=20 > I am trying to remove the arch-specific tlb_end_vma() and have a config > option to control this behavior. One thing worth noting is not all arm/arm64 hw versions support ranges. (system_supports_tlb_range()). But IIUC what you are trying to do, this isn't a problem. > Again, sorry for being slow. I hope to send an RFC soon. No worries. I brought it up only because I noticed it and didn't want it to slip away.