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24 Nov 2022 02:59:18 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 24 Nov 2022 02:59:14 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Thu, 24 Nov 2022 02:59:11 -0700 Date: Thu, 24 Nov 2022 09:58:53 +0000 From: Conor Dooley To: Samuel Ortiz CC: "Hongren (Zenithal) Zheng" , Palmer Dabbelt , Paul Walmsley , Albert Ou , Atish Patra , Anup Patel , Eric Biederman , Kees Cook , , , , , Michael Kerrisk , , Jiatai He , Heiko Stuebner Subject: Re: [PATCH v3 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: ARC-Seal: i=1; s=arc-20220608; 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dkim=pass header.d=microchip.com header.s=mchp header.b="VNP4rM/q"; spf=pass (imf09.hostedemail.com: domain of Conor.Dooley@microchip.com designates 68.232.154.123 as permitted sender) smtp.mailfrom=Conor.Dooley@microchip.com; dmarc=pass (policy=quarantine) header.from=microchip.com X-Rspamd-Server: rspam07 X-Stat-Signature: trq8s7ts6z1fzd4f8dixn8uyopgryxw8 X-HE-Tag: 1669283960-154776 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Thu, Nov 24, 2022 at 10:30:21AM +0100, Samuel Ortiz wrote: > On Mon, Jun 13, 2022 at 02:46:35AM +0800, Hongren (Zenithal) Zheng wrote: > > diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h > > index 46dc3f5ee99f..bfed3e5c338c 100644 > > --- a/arch/riscv/include/uapi/asm/hwcap.h > > +++ b/arch/riscv/include/uapi/asm/hwcap.h > > @@ -22,4 +22,26 @@ > > #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) > > #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) > > > > +/* > > + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 > > + * > > + * As only 32 bits of elf_hwcap (in kernel) could be used > > + * and RISC-V has reserved 26 bits of it, other caps like > > + * bitmanip and crypto can not be placed in AT_HWCAP > > + */ > > Have we agreed that multi-letter ISA extensions would use hwcap to be > exposed to userspace? With so many potential extensions, we could > quickly run out of space on AT_HWCAP2 as well. Palmer whipped up a PoC hwprobe interface (during Plumbers I think) that Heiko is currently looking into - I think his motivation is misaligned access performance. There's a branch but I have no idea if it even compiles... I'm mostly waiting for whatever Heiko comes up with ;) https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=riscv-hwprobe-v1 This patchset seems to need a rebase anyway per your other reply, but I guess that the new proposed interface would be preferable? Thanks, Conor.