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Wed, 2 Nov 2022 08:17:39 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id bgH+IqMnYmOBBQAAMHmgww (envelope-from ); Wed, 02 Nov 2022 08:17:39 +0000 Date: Wed, 2 Nov 2022 09:17:38 +0100 From: Michal Hocko To: "Huang, Ying" Cc: Bharata B Rao , Aneesh Kumar K V , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrew Morton , Alistair Popple , Dan Williams , Dave Hansen , Davidlohr Bueso , Hesham Almatary , Jagdish Gediya , Johannes Weiner , Jonathan Cameron , Tim Chen , Wei Xu , Yang Shi Subject: Re: [RFC] memory tiering: use small chunk size and more tiers Message-ID: References: <59291b98-6907-0acf-df11-6d87681027cc@linux.ibm.com> <8735b8jy9k.fsf@yhuang6-desk2.ccr.corp.intel.com> <0d938c9f-c810-b10a-e489-c2b312475c52@amd.com> <87tu3oibyr.fsf@yhuang6-desk2.ccr.corp.intel.com> <07912a0d-eb91-a6ef-2b9d-74593805f29e@amd.com> <87leowepz6.fsf@yhuang6-desk2.ccr.corp.intel.com> <878rkuchpm.fsf@yhuang6-desk2.ccr.corp.intel.com> <87bkppbx75.fsf@yhuang6-desk2.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87bkppbx75.fsf@yhuang6-desk2.ccr.corp.intel.com> ARC-Authentication-Results: i=1; imf21.hostedemail.com; dkim=pass header.d=suse.com header.s=susede1 header.b=jz9zThdt; spf=pass (imf21.hostedemail.com: domain of mhocko@suse.com designates 195.135.220.29 as permitted sender) smtp.mailfrom=mhocko@suse.com; dmarc=pass (policy=quarantine) header.from=suse.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1667377061; a=rsa-sha256; cv=none; b=Cagm3jLR5AK2vdIu8sTOhH6/QaxCc+W8TzFBk/lnTWOXAVKQPfeyEJJ/7+lv99KV8cFFCb c7nSYPiHWj/XTmlfgip5eDzWKNlA+Ij4BnxNowivCBNNHdue4kOUd4vOjDAafuIE5F7ArI G9kKHSnLXFQJA35Aoh9mIo1bvRUjBFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1667377061; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=wko95XSy2SHsBUnksXP59GvfWwdvJCJ/BihoSvq6r4o=; b=ESjQ0wRcBmFRNGDu//CMK5GF0azSa8cvj4Mmb0YnoSqXG5fJH9Jb8tMXDZtYNRWhPkg9mk KikaBXJVCGtj6q+BGaJ3YjUMLYiCU0ILco1oV8HhrfiOKl9O/mLLPQDl4Oq06lkFbTxB1u MfGDD8Hl1Gz6sGzMh7CZzdCHh1m4NOg= X-Stat-Signature: ks7zwz4mpqnskgniugu9pwphjbz5nksh X-Rspamd-Queue-Id: 2ED3A1C0008 Authentication-Results: imf21.hostedemail.com; dkim=pass header.d=suse.com header.s=susede1 header.b=jz9zThdt; spf=pass (imf21.hostedemail.com: domain of mhocko@suse.com designates 195.135.220.29 as permitted sender) smtp.mailfrom=mhocko@suse.com; dmarc=pass (policy=quarantine) header.from=suse.com X-Rspam-User: X-Rspamd-Server: rspam12 X-HE-Tag: 1667377060-310172 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed 02-11-22 16:02:54, Huang, Ying wrote: > Michal Hocko writes: > > > On Wed 02-11-22 08:39:49, Huang, Ying wrote: > >> Michal Hocko writes: > >> > >> > On Mon 31-10-22 09:33:49, Huang, Ying wrote: > >> > [...] > >> >> In the upstream implementation, 4 tiers are possible below DRAM. That's > >> >> enough for now. But in the long run, it may be better to define more. > >> >> 100 possible tiers below DRAM may be too extreme. > >> > > >> > I am just curious. Is any configurations with more than couple of tiers > >> > even manageable? I mean applications have been struggling even with > >> > regular NUMA systems for years and vast majority of them is largerly > >> > NUMA unaware. How are they going to configure for a more complex system > >> > when a) there is no resource access control so whatever you aim for > >> > might not be available and b) in which situations there is going to be a > >> > demand only for subset of tears (GPU memory?) ? > >> > >> Sorry for confusing. I think that there are only several (less than 10) > >> tiers in a system in practice. Yes, here, I suggested to define 100 (10 > >> in the later text) POSSIBLE tiers below DRAM. My intention isn't to > >> manage a system with tens memory tiers. Instead, my intention is to > >> avoid to put 2 memory types into one memory tier by accident via make > >> the abstract distance range of each memory tier as small as possible. > >> More possible memory tiers, smaller abstract distance range of each > >> memory tier. > > > > TBH I do not really understand how tweaking ranges helps anything. > > IIUC drivers are free to assign any abstract distance so they will clash > > without any higher level coordination. > > Yes. That's possible. Each memory tier corresponds to one abstract > distance range. The larger the range is, the higher the possibility of > clashing is. So I suggest to make the abstract distance range smaller > to reduce the possibility of clashing. I am sorry but I really do not understand how the size of the range actually addresses a fundamental issue that each driver simply picks what it wants. Is there any enumeration defining basic characteristic of each tier? How does a driver developer knows which tear to assign its driver to? -- Michal Hocko SUSE Labs